https://github.com/proppy/tinytapeout-xls-inverter
https://github.com/proppy/tinytapeout-xls-inverter
tinytapeout
Last synced: over 1 year ago
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- Host: GitHub
- URL: https://github.com/proppy/tinytapeout-xls-inverter
- Owner: proppy
- License: apache-2.0
- Created: 2022-08-31T09:12:51.000Z (almost 4 years ago)
- Default Branch: main
- Last Pushed: 2022-09-23T00:24:50.000Z (almost 4 years ago)
- Last Synced: 2025-01-30T05:13:21.914Z (over 1 year ago)
- Topics: tinytapeout
- Language: Jupyter Notebook
- Homepage:
- Size: 243 KB
- Stars: 0
- Watchers: 2
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- Funding: .github/FUNDING.yml
- License: LICENSE
Awesome Lists containing this project
README
# XLS template for TinyTapeout
Template for submitting [TinyTapeout](https://tinytapeout.com) designs based on [XLS: Accelerated HW Synthesis](https://github.com/google/xls) toolkit .
## Example
### DSLX input
```
fn inverter(n: u8) -> u8 {
!n
}
#![test]
fn popcount_test() {
let _= assert_eq(inverter(u8:0b0000_0000), u8:0b1111_1111);
let _= assert_eq(inverter(u8:0b0000_0001), u8:0b1111_1110);
let _= assert_eq(inverter(u8:0b1111_0000), u8:0b0000_1111);
let _= assert_eq(inverter(u8:0b0101_0101), u8:0b1010_1010);
let _= assert_eq(inverter(u8:0b1111_1111), u8:0b0000_0000);
_
}
pub fn user_module(io_in: u8) -> u8 {
inverter(io_in)
}
```
### Verilog output
```
module user_module_339800239192932947(
input wire [7:0] io_in,
output wire [7:0] out
);
assign out = ~io_in;
endmodule
```
# How to change the Wokwi project
Edit the [Makefile](Makefile) and change the WOKWI_PROJECT_ID to match your project.
# What is this about?
This repo is a template you can make a copy of for your own [ASIC](https://www.zerotoasiccourse.com/terminology/asic/) design using [Wokwi](https://wokwi.com/).
When you edit the Makefile to choose a different ID, the [GitHub Action](.github/workflows/wokwi.yaml) will fetch the digital netlist of your design from Wokwi.
The design gets wrapped in some extra logic that builds a 'scan chain'. This is a way to put lots of designs onto one chip and still have access to them all. You can see [all of the technical details here](https://github.com/mattvenn/scan_wrapper).
After that, the action uses the open source ASIC tool called [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/) to build the files needed to fabricate an ASIC.
# What files get made?
When the action is complete, you can [click here](https://github.com/mattvenn/wokwi-verilog-gds-test/actions) to see the latest build of your design. You need to download the zip file and take a look at the contents:
* gds_render.svg - picture of your ASIC design
* gds.html - zoomable picture of your ASIC design
* runs/wokwi/reports/final_summary_report.csv - CSV file with lots of details about the design
* runs/wokwi/reports/synthesis/1-synthesis.stat.rpt.strategy4 - list of the [standard cells](https://www.zerotoasiccourse.com/terminology/standardcell/) used by your design
* runs/wokwi/results/final/gds/user_module.gds - the final [GDS](https://www.zerotoasiccourse.com/terminology/gds2/) file needed to make your design
# What next?
* Share your GDS on twitter, tag it #tinytapeout and [link me](https://twitter.com/matthewvenn)!
* [Submit it to be made](https://docs.google.com/forms/d/e/1FAIpQLSc3ZF0AHKD3LoZRSmKX5byl-0AzrSK8ADeh0DtkZQX0bbr16w/viewform?usp=sf_link)
* [Join the community](https://discord.gg/rPK2nSjxy8)