https://github.com/pseudoincorrect/verilog_labs
Verilog labs
https://github.com/pseudoincorrect/verilog_labs
c dsp soft-cpu verilog
Last synced: about 1 year ago
JSON representation
Verilog labs
- Host: GitHub
- URL: https://github.com/pseudoincorrect/verilog_labs
- Owner: pseudoincorrect
- Created: 2018-12-02T09:48:07.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2018-12-02T09:50:32.000Z (over 7 years ago)
- Last Synced: 2025-02-09T09:09:53.748Z (over 1 year ago)
- Topics: c, dsp, soft-cpu, verilog
- Language: C
- Homepage:
- Size: 6.95 MB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files: