https://github.com/pseudoincorrect/verilog_labs

Verilog labs
https://github.com/pseudoincorrect/verilog_labs

c dsp soft-cpu verilog

Last synced: about 23 hours ago
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Verilog labs

• Host: GitHub
• URL: https://github.com/pseudoincorrect/verilog_labs
• Owner: pseudoincorrect
• Created: 2018-12-02T09:48:07.000Z (about 6 years ago)
• Default Branch: master
• Last Pushed: 2018-12-02T09:50:32.000Z (about 6 years ago)
• Last Synced: 2024-12-16T23:34:25.161Z (about 2 months ago)
• Topics: c, dsp, soft-cpu, verilog
• Language: C
• Homepage:
• Size: 6.95 MB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:

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