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https://github.com/pulp-platform/FlooNoC
A Fast, Low-Overhead On-chip Network
https://github.com/pulp-platform/FlooNoC
Last synced: 3 months ago
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A Fast, Low-Overhead On-chip Network
- Host: GitHub
- URL: https://github.com/pulp-platform/FlooNoC
- Owner: pulp-platform
- License: apache-2.0
- Created: 2023-06-19T14:09:30.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2024-04-22T11:09:56.000Z (7 months ago)
- Last Synced: 2024-04-22T11:32:09.521Z (7 months ago)
- Language: SystemVerilog
- Homepage:
- Size: 3.96 MB
- Stars: 69
- Watchers: 6
- Forks: 10
- Open Issues: 5
-
Metadata Files:
- Readme: README.md
- Changelog: CHANGELOG.md
- License: LICENSE-APACHE
- Citation: CITATION.cff
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README
# FlooNoC: A Fast, Low-Overhead On-chip Network
This repository provides modules for the FlooNoC, a Network-on-Chip (NoC) which is part of the [PULP (Parallel Ultra-Low Power) Platform](https://pulp-platform.org/). The repository includes Network Interface IPs (named chimneys), Routers and further NoC components to build a complete NoC. FlooNoC mainly supports [AXI4+ATOPs](https://github.com/pulp-platform/axi/tree/master), but can be easily extended to other On-Chip protocols. Arbitrary topologies are supported with several routing algorithms. FlooNoC is designed to be scalable and modular, and can be easily extended with new components. Additionally, FlooNoC provides a generation framework for creating customized NoC configurations.
[](https://github.com/pulp-platform/FlooNoC/actions/workflows/gitlab-ci.yml?query=branch%3Amain)
[](CHANGELOG.md)
[Design Principles](#-design-principles) •
[Getting started](#-getting-started) •
[List of IPs](#-list-of-ips) •
[Generation](#%EF%B8%8F-generation) •
[License](#-license)
## 💡 Design Principles
Our NoC design is grounded in the following key principles:
1. **Full AXI4 Support**: Our design fully supports AXI4+ATOPs from AXI5 as outlined [here](https://github.com/pulp-platform/axi/tree/master), particularly multiple outstanding burst transactions. It utilizes low-complexity routers and a decoupled link-level protocol to ensure scalability, thereby enabling tolerance to high-latency off-chip accesses.
1. **Decoupled Links and Networks**: We use a link-level protocol that is decoupled from the network-level protocol. This allows us to move the complexity of the network-level protocol into the network interfaces, while deploying low-complexity routers in the network, that enable better scalability.
1. **Wide Physical Channels**: We incorporate wide physical channels in order to meet the high-bandwidth requirements at network endpoints without being constrained by the operating frequency. This is in contrast to the traditional narrow link approach. Further, the NoC avoids any kind of serialization and sends entire messages in a single flit including header and tail information.
1. **Separation of traffic**: Our design acknowledges the diversity in traffic patterns, as it decouples links and networks to handle wide, high-bandwidth, burst-based traffic and narrow, latency-sensitive traffic with separate physical channels.
1. **Modularity:** Our design principles also emphasize modularity. We have developed a set of IPs that can be instantiated together to build a NoC. This approach not only promotes reusability but also facilitates flexibility in designing custom NoCs to cater to a variety of specific system requirements.
## 🔮 Origin of the name
The names of the IPs are inspired by the [Harry Potter](https://en.wikipedia.org/wiki/Harry_Potter) universe, where the [Floo Network](https://harrypotter.fandom.com/wiki/Floo_Network) is a magical transportation system. The Network interfaces are named after the fireplaces and chimneys used to access the Floo Network.
> In use for centuries, the Floo Network, while somewhat uncomfortable, has many advantages. Firstly, unlike broomsticks, the Network can be used without fear of breaking the International Statute of Secrecy. Secondly, unlike Apparition, there is little to no danger of serious injury. Thirdly, it can be used to transport children, the elderly and the infirm."
## 🔐 License
All code checked into this repository is made available under a permissive license. All software sources are licensed under the Apache License 2.0 (see [`LICENSE-APACHE`](LICENSE-APACHE)), and all hardware sources in the `hw` folder are licensed under the Solderpad Hardware License 0.51 (see [`LICENSE-SHL`](LICENSE-SHL)).
## 📚 Publication
If you use FlooNoC in your research, please cite the following paper:
FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic
```
@misc{fischer2023floonoc,
title={FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic},
author={Tim Fischer and Michael Rogenmoser and Matheus Cavalcante and Frank K. Gürkaynak and Luca Benini},
year={2023},
eprint={2305.08562},
archivePrefix={arXiv},
primaryClass={cs.AR}
}
```
## ⭐ Getting Started
### Pre-requisites
FlooNoC uses [bender](https://github.com/pulp-platform/bender) to manage its dependencies and to automatically generate compilation scripts. Further `Python >= 3.10` is required to install the generation framework.
### Simulation
Currently, we do not provide any open-source simulation setup. Internally, the FlooNoC was tested using QuestaSim, which can be launched with the following command:
```sh
# Compile the sources
make compile-sim
# Run the simulation
make run-sim-batch VSIM_TB_DUT=tb_floo_dut
```
or in the GUI, with prepared waveforms:
```sh
# Compile the sources
make compile-sim
# Run the simulation
make run-sim VSIM_TB_DUT=tb_floo_dut
```
By replacing `tb_floo_dut` with the name of the testbench you want to simulate.
## 🧰 List of IPs
This repository includes the following NoC IPs:
1. **Routers:** A collection of different NoC router designs with varying features such as virtual channels, input/output buffering, and adaptive routing algorithms.
1. **Network Interfaces (NIs)**: A set of NoC network interfaces for connecting IPs to the NoC.
1. **Topologies:** A collection of NoC topologies, such as mesh, to enable the creation of various on-chip interconnects.
1. **Common IPs** A set of IPs used by the NoC IPs, such as FIFOs, Cuts and arbiters.
1. **Verification IPs (VIPs):** A set of VIPs to verify the correct functionality of the NoC IPs.
1. **Testbenches:** A set of testbenches to evaluate the performance of the NoC IPs, including throughput, latency.
### Routers
| Name | Description | Doc |
| --- | --- | --- |
| [floo_router](hw/floo_router.sv) | A simple router with configurable number of ports, physical and virtual channels, and input/output buffers | |
| [floo_narrow_wide_router](hw/floo_narrow_wide_router.sv) | Wrapper of a multi-link router for narrow and wide links | |
### Network Interfaces
| Name | Description | Doc |
| --- | --- | --- |
| [floo_axi_chimney](hw/floo_axi_chimney.sv) | A bidirectional network interface for connecting AXI4 Buses to the NoC | |
| [floo_narrow_wide_chimney](hw/floo_narrow_wide_chimney.sv) | A bidirectional network interface for connecting narrow & wide AXI Buses to the multi-link NoC | |
### Topologies
| Name | Description | Doc |
| --- | --- | --- |
| [floo_mesh](hw/floo_mesh.sv) | A mesh topology with configurable number of rows and columns | |
| [floo_mesh_ruche](hw/floo_mesh_ruche.sv) | A mesh topology with ruche channels and a configurable number of rows and columns | |
### Common IPs
| Name | Description | Doc |
| --- | --- | --- |
| [floo_fifo](hw/floo_fifo.sv) | A FIFO buffer with configurable depth | |
| [floo_cut](hw/floo_cut.sv) | Elastic buffers for cuting timing paths | |
| [floo_cdc](hw/floo_cdc.sv) | A Clock-Domain-Crossing (CDC) module implemented with a gray-counter based FIFO. | |
| [floo_wormhole_arbiter](hw/floo_wormhole_arbiter.sv) | A wormhole arbiter | |
| [floo_vc_arbiter](hw/floo_vc_arbiter.sv) | A virtual channel arbiter | |
| [floo_route_comp](hw/floo_route_comp.sv) | A helper module to compute the packet destination | |
| [floo_rob](hw/floo_rob.sv) | A table-based Reorder Buffer | |
| [floo_simple_rob](hw/floo_simple_rob.sv) | A simplistic low-complexity Reorder Buffer | |
| [floo_rob_wrapper](hw/floo_simple_rob.sv) | A wrapper of all available types of RoBs including RoB-less version | |
| [floo_narrow_wide_join](hw/floo_narrow_wide_join.sv) | A mux for joining a narrow and wide AXI bus a single wide bus | |
### Verification IPs
| Name | Description | Doc |
| --- | --- | --- |
| [axi_bw_monitor](hw/test/axi_bw_monitor.sv) | A AXI4 Bus Monitor for measuring the throughput and latency of the AXI4 Bus | |
| [axi_reorder_compare](hw/test/axi_reorder_compare.sv) | A AXI4 Bus Monitor for verifying the order of AXI transactions with the same ID | |
| [floo_axi_rand_slave](hw/test/floo_axi_rand_slave.sv) | A AXI4 Bus Multi-Slave generating random AXI respones with configurable response time | |
| [floo_axi_test_node](hw/test/floo_axi_test_node.sv) | A AXI4 Bus Master-Slave Node for generating random AXI transactions | |
| [floo_dma_test_node](hw/test/floo_dma_test_node.sv) | An endpoint node with a DMA master port and a Simulation Memory Slave port | |
| [floo_hbm_model](hw/test/floo_hbm_model.sv) | A very simple model of the HBM memory controller with configurable delay | |
## 🛠️ Generation
FlooNoC comes with a generation framework called `floogen`. It allows to create complex network configurations with a simple configuration file.
### Capabilities
`floogen` has a graph-based internal representation of the network configuration. This allows to easily add new features and capabilities to the generation framework. The following list shows the a couple of the current capabilities of `floogen`:
- **Validation**: The configuration is validated before the generation to ensure that the configuration is valid. For instance, the configuration is checked for invalid user input, overlapping address ranges
- **Routing**: XY-Routing and ID-Table routing are supported. `floogen` automatically generates the routing tables for the routers, as well as the address map for the network interfaces.
- **Package Generation**: `floogen` automatically generates a SystemVerilog package with all the needed types and constants for the network configuration.
- **Top Module Generation**: `floogen` automatically generates a top module that contains all router and network interfaces. The interfaces of the top module are AXI4 interfaces for all the enpdoints specified in the configuration.
### Example
The following example shows the configuration for a simple mesh topology with 4x4 routers and 4x4 chimneys with XY-Routing.
```yaml
name: example_system
description: "Example of a configuration file"
routing:
route_algo: "XY"
use_id_table: true
protocols:
- name: "example_axi"
type: "AXI4"
direction: "manager"
data_width: 64
addr_width: 32
id_width: 3
user_width: 1
- name: "example_axi"
type: "AXI4"
direction: "subordinate"
data_width: 64
addr_width: 32
id_width: 3
user_width: 1
endpoints:
- name: "cluster"
array: [4, 4]
addr_range:
base: 0x1000_0000
size: 0x0004_0000
mgr_port_protocol:
- "example_axi"
sbr_port_protocol:
- "example_axi"
routers:
- name: "router"
array: [4, 4]
connections:
- src: "cluster"
dst: "router"
src_range:
- [0, 3]
- [0, 3]
dst_range:
- [0, 3]
- [0, 3]
bidirectional: true
```
### Usage
To install `floogen` run the following command:
```sh
pip install .
```
which allows you to use `floogen` with the following command:
```sh
floogen -c -o
```
### Configuration
The example configuration above shows the basic structure of a configuration file. A more detailed description of the configuration file can be found in the [documentation](docs/floogen.md).