https://github.com/pulp-platform/axi_mem_if
Simple single-port AXI memory interface
https://github.com/pulp-platform/axi_mem_if
asic axi fpga systemverilog-hdl
Last synced: 5 months ago
JSON representation
Simple single-port AXI memory interface
- Host: GitHub
- URL: https://github.com/pulp-platform/axi_mem_if
- Owner: pulp-platform
- License: other
- Created: 2018-02-05T11:52:18.000Z (over 8 years ago)
- Default Branch: master
- Last Pushed: 2022-01-25T18:02:30.000Z (over 4 years ago)
- Last Synced: 2023-02-28T17:11:57.401Z (over 3 years ago)
- Topics: asic, axi, fpga, systemverilog-hdl
- Language: SystemVerilog
- Size: 62.5 KB
- Stars: 19
- Watchers: 7
- Forks: 19
- Open Issues: 3
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Metadata Files:
- Changelog: CHANGELOG.md
- License: LICENSE