https://github.com/pulp-platform/axi_node

AXI X-Bar
https://github.com/pulp-platform/axi_node

asic axi fpga systemverilog

Last synced: about 2 months ago
JSON representation

AXI X-Bar

• Host: GitHub
• URL: https://github.com/pulp-platform/axi_node
• Owner: pulp-platform
• License: other
• Archived: true
• Created: 2016-02-18T18:20:35.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2020-04-08T13:51:15.000Z (over 4 years ago)
• Last Synced: 2024-06-15T22:37:06.294Z (3 months ago)
• Topics: asic, axi, fpga, systemverilog
• Language: SystemVerilog
• Homepage:
• Size: 187 KB
• Stars: 18
• Watchers: 6
• Forks: 35
• Open Issues: 6
• Metadata Files:
  • Readme: README.md
  • Changelog: CHANGELOG.md
  • License: LICENSE

Awesome Lists containing this project

README

        
# AXI Interconnect

This repository has been archived. A fully AXI compliant replacement for this interconnect can be found in [pulp-platform/axi](https://github.com/pulp-platform/axi).