https://github.com/pulp-platform/cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
https://github.com/pulp-platform/cheshire

asic fpga riscv rtl-design simulation systemverilog

Last synced: about 2 months ago
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A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

• Host: GitHub
• URL: https://github.com/pulp-platform/cheshire
• Owner: pulp-platform
• License: other
• Created: 2022-09-01T07:39:26.000Z (about 2 years ago)
• Default Branch: main
• Last Pushed: 2024-06-06T16:42:15.000Z (3 months ago)
• Last Synced: 2024-06-08T03:22:23.040Z (3 months ago)
• Topics: asic, fpga, riscv, rtl-design, simulation, systemverilog
• Language: SystemVerilog
• Homepage:
• Size: 29.8 MB
• Stars: 136
• Watchers: 14
• Forks: 31
• Open Issues: 26
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

        
# Cheshire

Cheshire is a minimal Linux-capable host platform built around the RISC-V [CVA6](https://github.com/openhwgroup/cva6) core. Its goal is to provide a *lightweight*, *configurable*, *autonomously booting* host to systems that need one, from minimal Linux-capable SoCs to manycore compute accelerators.

Cheshire is developed as part of the PULP project, a joint effort between ETH Zurich and the University of Bologna.

## Quick Start

* To learn how to build and use Cheshire, see [Getting Started](https://pulp-platform.github.io/cheshire/gs/).

* To learn about available simulation, FPGA, and ASIC targets, see [Targets](https://pulp-platform.github.io/cheshire/tg).

* For detailed information on Cheshire's inner workings, consult the [User Manual](https://pulp-platform.github.io/cheshire/um/).

If you are impatient and have all needed [dependencies](https://pulp-platform.github.io/cheshire/gs/#dependencies), you can run `make all`, then start QuestaSim in `target/sim/vsim` and run a [simulation](https://pulp-platform.github.io/cheshire/tg/sim) by typing:

```

set BINARY ../../../sw/tests/helloworld.spm.elf

source compile.cheshire_soc.tcl

source start.cheshire_soc.tcl

run -all

```

## License

Unless specified otherwise in the respective file headers, all code checked into this repository is made available under a permissive license. All hardware sources and tool scripts are licensed under the Solderpad Hardware License 0.51 (see `LICENSE`) or compatible licenses. Register file code (e.g. `hw/regs/*.sv`) is generated by a fork of lowRISC's [`regtool`](https://github.com/lowRISC/opentitan/blob/master/util/regtool.py) and licensed under Apache 2.0. The USB OHCI controller (`hw/future/UsbOhciAxi4.v`) is generated from the [SpinalHDL](https://github.com/SpinalHDL/SpinalHDL) library licensed under the MIT license. All software sources are licensed under Apache 2.0.

## Publication

If you use Cheshire in your work, you can cite us:

```

@article{ottaviano2023cheshire,

      title   = {Cheshire: A Lightweight, Linux-Capable RISC-V Host

                 Platform for Domain-Specific Accelerator Plug-In},

      author  = {Alessandro Ottaviano and Thomas Benz and

                 Paul Scheffler and Luca Benini},

      journal = {IEEE Transactions on Circuits and Systems II: Express Briefs},

      year    = {2023},

      volume  = {70},

      number  = {10},

      pages   = {3777-3781},

      doi     = {10.1109/TCSII.2023.3289186}

}

```