https://github.com/pulp-platform/common_verification
SystemVerilog modules and classes commonly used for verification
https://github.com/pulp-platform/common_verification
Last synced: 5 months ago
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SystemVerilog modules and classes commonly used for verification
- Host: GitHub
- URL: https://github.com/pulp-platform/common_verification
- Owner: pulp-platform
- License: other
- Created: 2019-01-10T08:44:13.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2025-01-07T15:19:58.000Z (over 1 year ago)
- Last Synced: 2025-03-21T10:23:42.371Z (over 1 year ago)
- Language: SystemVerilog
- Size: 49.8 KB
- Stars: 46
- Watchers: 7
- Forks: 14
- Open Issues: 2
-
Metadata Files:
- Readme: README.md
- Changelog: CHANGELOG.md
- License: LICENSE
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README
# Common Verification
This repository contains commonly used SystemVerilog modules and classes for verification. This
code is generally not synthesizable.
## Contents
### Basic Modules
| Name | Description | Status |
|----------------------|----------------------------------------------------------------------------|--------|
| `clk_rst_gen` | Standalone clock and reset generator | active |
| `sim_timeout` | Timeout for simulations | active |
| `stream_watchdog` | Terminates a simulation after a number of cycles of inactivity of a stream | active |
### Generic Functions and Tasks
`rand_verif_pkg` defines the following functions and tasks:
| Name | Description | Status |
|---------------------|-------------------------------------------------------------|--------|
| `rand_wait` | Wait for a random number (within interval) of clock cycles | active |
### Simple Synchronous Drivers
| Name | Description | Status |
|-------------------------------|---------------------------------------------------|--------|
| `rand_synch_driver` | Randomizing synchronous driver | active |
| `rand_synch_holdable_driver` | Randomizing synchronous driver that can be halted | active |
### Stream (Ready/Valid) Masters and Slaves
| Name | Description | Status |
|-------------------|---------------------------------------|--------|
| `rand_stream_mst` | Randomizing stream master | active |
| `rand_stream_slv` | Randomizing stream slave | active |
### Data Structures
| Name | Description | Status |
|-------------------|---------------------------------------|--------|
| `rand_id_queue` | ID queue with randomizing output | active |
### Simulation Helpers
| Name | Description | Status |
|----------------------|-------------------------------------------------------|--------|
| `signal_highlighter` | Highlights a signal in the wave for better visibility | active |