https://github.com/pulp-platform/croc

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
https://github.com/pulp-platform/croc

asic riscv rtl-design systemverilog

Last synced: about 1 month ago
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A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

• Host: GitHub
• URL: https://github.com/pulp-platform/croc
• Owner: pulp-platform
• License: other
• Created: 2024-07-18T08:30:13.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2026-01-23T17:10:01.000Z (about 2 months ago)
• Last Synced: 2026-01-30T22:59:15.619Z (about 2 months ago)
• Topics: asic, riscv, rtl-design, systemverilog
• Language: SystemVerilog
• Homepage: https://pulp-platform.github.io/croc/
• Size: 107 MB
• Stars: 200
• Watchers: 5
• Forks: 90
• Open Issues: 16
• Metadata Files:
  • Readme: README.md
  • Changelog: CHANGELOG.md
  • License: LICENSE.md

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