https://github.com/pulp-platform/culsans
Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
https://github.com/pulp-platform/culsans
Last synced: 5 months ago
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Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
- Host: GitHub
- URL: https://github.com/pulp-platform/culsans
- Owner: pulp-platform
- License: other
- Created: 2022-09-05T05:54:46.000Z (almost 4 years ago)
- Default Branch: master
- Last Pushed: 2024-05-04T08:39:59.000Z (about 2 years ago)
- Last Synced: 2025-04-20T07:41:14.923Z (about 1 year ago)
- Language: C
- Homepage:
- Size: 1.38 MB
- Stars: 30
- Watchers: 5
- Forks: 12
- Open Issues: 2
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# Culsans - tightly-coupled cache coherence unit using the ACE protocol
## Introduction
Aim of this project is the development of a tightly-coupled cache coherence unit for a multicore processor based on
[CVA6](https://github.com/openhwgroup/cva6). Like the ancient god [^1], its responsibilities are to maintain order
(and data consistency) among the memory accesses performed by the 2~4 CPUs which are part of the system.
[^1]: [Culsans](https://en.wikipedia.org/wiki/Culsans) – the Etruscan version of [Janus](https://en.wikipedia.org/wiki/Janus),
the two-faced and also four-faced god, god of the first and last of the year, of the beginning and the end, of the
cardinal points and thus of order in general.
## Getting started
```
git clone https://github.com/planvtech/culsans.git --recursive
```
Useful documentation:
- [CVA6's coherent WB cache](https://github.com/planvtech/cva6/blob/culsans_pulp/docs/03_cva6_design/wb_cache_with_coherence_support.md)
- [ACE Interconnector](https://github.com/planvtech/ace/blob/pulp/doc/ace_ccu_top.md)
- Testing (see below)
### Synthesis on FPGA (Genesys2)
```
make fpga
```
The top level file for FPGA synthesis is [`rtl/src/culsans_xilinx.sv`](rtl/src/culsans_xilinx.sv)
### SD image generation
Make sure all dependencies specified in [`cva6-sdk`](https://github.com/planvtech/cva6-sdk/blob/culsans_pulp/README.md) are fulfilled.
```
make sdk
```
Then follow the instruction in [`cva6-sdk`](https://github.com/planvtech/cva6-sdk/blob/culsans_pulp/README.md) to copy the generated image to the SD.
### RTL tests
Sanity check
```
make sanity-tests
```
Regression tests
```
make test
```
## Verification
### Culsans Integration Test Suite (CITS)
The CITS is a test platform that tests the integration of components of Culsans.
There are two layers to the tests.
There is c code self testing. This is achieved by c code within the test testing what it expects it has effected in the
memory. If it fails, it exits early with a code indicative of the core and cacheline that incurred the problem.
The second (optional) layer is that where an external parser inspects the logs generated by the tests and compares them to an
expected sequence. This layer is not further described here.
#### Running tests
Tests are run in the [`tests/integration`](tests/integration) directory. All commands below are executed in this directory.
To run a test in the CITS, type
```
make -C testlist/ all
```
To run a test in the CITS in a GUI, type
```
make GUI=1 -C testlist/ all
```
#### Adding tests
A CITS test consists of a batch of files within the folder `testlist/`. The folder should contain the following files:
| File | Description |
|-----------------|-------------|
| .c/h | This file is the the actual test. See similar files in the CITS for an example of how to write one. |
| main.c | This file co-ordinates the core execution and calls the `test_name()` function. See the `main.c` files in the CITS for an example on how to write one. |
| Makefile | Symlink to `../../test_automation/Makefile` |
| sim.tcl | Symlink to `../../test_automation/sim.tcl` |
The test function defined in .c should be self-checking and call `exit(arg)` with arg > 0 if the test fails, otherwise `return 0`.
## License
The Culsans repository is released under Solderpad v0.51 (SHL-0.51) see [LICENSE](LICENSE)