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https://github.com/pulp-platform/register_interface
Generic Register Interface (contains various adapters)
https://github.com/pulp-platform/register_interface
Last synced: about 2 months ago
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Generic Register Interface (contains various adapters)
- Host: GitHub
- URL: https://github.com/pulp-platform/register_interface
- Owner: pulp-platform
- License: other
- Created: 2018-09-17T15:10:35.000Z (almost 6 years ago)
- Default Branch: master
- Last Pushed: 2024-03-14T22:08:52.000Z (6 months ago)
- Last Synced: 2024-06-15T22:36:54.887Z (3 months ago)
- Language: SystemVerilog
- Homepage:
- Size: 756 KB
- Stars: 87
- Watchers: 6
- Forks: 20
- Open Issues: 1
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Metadata Files:
- Readme: README.md
- Changelog: CHANGELOG.md
- License: LICENSE
Awesome Lists containing this project
README
# Generic Register Interface
This repository contains a simple register interface definition as well as protocol adapters from APB, AXI-Lite, and AXI to said interface. Furthermore, it allows to generate a uniform register interface.
## Read Timing
![Read Timing](docs/timing_read.png)
## Write Timing
![Write Timing](docs/timing_write.png)
## Register File Generator
We re-use lowrisc's register file generator to generate arbitrary configuration registers from an `hjson` description. See the the [tool's description](https://docs.opentitan.org/doc/rm/register_tool/) for further usage details.
We use the [bender import tool](https://github.com/pulp-platform/bender#import-----copy-files-from-dependencies-that-do-not-support-bender) (`>v0.26.0`) to get the sources and apply our custom patches on top.
curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh -s -- 0.26.0
./bender import --refetchto re-vendor.