https://github.com/quanoom/frequencydivider
verilog code for frequency divider circuit implemented with verilog hdl
https://github.com/quanoom/frequencydivider
digital-design fpga frequency-divider hardware-description-language hdl verilog
Last synced: 4 months ago
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verilog code for frequency divider circuit implemented with verilog hdl
- Host: GitHub
- URL: https://github.com/quanoom/frequencydivider
- Owner: Quanoom
- License: mit
- Created: 2024-12-03T15:41:38.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2025-04-14T13:01:35.000Z (about 1 year ago)
- Last Synced: 2026-01-30T20:55:50.183Z (5 months ago)
- Topics: digital-design, fpga, frequency-divider, hardware-description-language, hdl, verilog
- Language: Verilog
- Homepage:
- Size: 8.79 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
#### Frequency divider with verilog :
frequency divider circuit that outputs three different clocks with(50 Khz, 100 Khz and 250 Khz).
* Clock 1 : 250 Khz
* Clock 2 : 100 Khz
* Clock 3 : 50 Khz
the verilog code was tested in ModelSim using ModelSim simulator, you can check the simulation by reviewing the [@simulation](https://github.com/0xaB26/FrequencyDivider/blob/main/wave)