https://github.com/quartiq/mirny

CPLD gateware for the Sinara Mirny module.
https://github.com/quartiq/mirny

artiq cpld fpga migen sinara-hw

Last synced: about 1 month ago
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CPLD gateware for the Sinara Mirny module.

• Host: GitHub
• URL: https://github.com/quartiq/mirny
• Owner: quartiq
• License: gpl-3.0
• Created: 2019-06-16T18:44:51.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2024-08-20T15:40:20.000Z (4 months ago)
• Last Synced: 2024-08-20T17:39:14.788Z (4 months ago)
• Topics: artiq, cpld, fpga, migen, sinara-hw
• Language: Python
• Homepage:
• Size: 35.2 KB
• Stars: 0
• Watchers: 3
• Forks: 3
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE.GPL-3

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README

        
# Mirny CPLD gateware

## Hardware

[![Hardware](https://github.com/sinara-hw/mirny/wiki/Mirny_v1.0_top_small.jpg)](https://github.com/sinara-hw/mirny/wiki)

[Mirny Schematics](https://github.com/sinara-hw/mirny/releases)

## Building

Needs [migen](https://github.com/m-labs/migen) and [Xilinx ISE](https://www.xilinx.com/products/design-tools/ise-design-suite.html). Assumes ISE is installed in ``/opt/Xilinx``.

```

make

```

## Flashing

With Digilent [JTAG HS2](https://store.digilentinc.com/jtag-hs2-programming-cable/) cable:

  - download firmware to dongle. Manually (adjust USB bus as needed):

  ```

  /sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-3/devnum`

  ```

  or automatically via the ``udev`` rule:

  ```

  SUBSYSTEM=="usb", ACTION="add", ATTR{idVendor}=="0403", ATTR{idProduct}=="6014", ATTR{manufacturer}=="Digilent", RUN+="/usr/bin/fxload -v -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D $tempnode"

  ```

  - install [xc3sprog](http://xc3sprog.sourceforge.net/)

  - ``flash_xc3.sh jtaghs2``

  - look for ``Verify: Success``

# License

GPLv3+