https://github.com/racerxdl/fpga-serial-hello
FPGA Verilog Serial Hello World + Led Blink
https://github.com/racerxdl/fpga-serial-hello
arduino fpga hello-world lattice led-blink verilog yosis
Last synced: 6 months ago
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FPGA Verilog Serial Hello World + Led Blink
- Host: GitHub
- URL: https://github.com/racerxdl/fpga-serial-hello
- Owner: racerxdl
- Created: 2020-06-14T05:55:22.000Z (over 5 years ago)
- Default Branch: master
- Last Pushed: 2020-06-14T05:56:29.000Z (over 5 years ago)
- Last Synced: 2025-03-24T22:42:13.949Z (7 months ago)
- Topics: arduino, fpga, hello-world, lattice, led-blink, verilog, yosis
- Language: Verilog
- Size: 4.88 KB
- Stars: 7
- Watchers: 2
- Forks: 4
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
FPGA Serial Hello World
=========================
All files are licensed in Apache except for `SerialRX.v` and `SerialTX.v` which are from FPGA4FUN.
This examples compiles a FPGA Core that prints out `Hello World\n` on serial port and blinks a led with fade-in.
This example is tuned to work on [Colorlight Hub 5a-75b v6.1](https://github.com/q3k/chubby75/blob/master/5a-75b/hardware_V6.1.md).
The LED is connected to onboard D2 LED (FPGA PIN U16), TXD to J4 Pin 1 (FPGA Pin N3), RXD to J4 Pin 2 (FPGA Pin N4), clk connected to onboard clock (FPGA PIN P3)
Running `make` will trigger the build of svf file using docker.