https://github.com/racerxdl/lvds-7-to-1-serializer

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.
https://github.com/racerxdl/lvds-7-to-1-serializer

fpga lcd lvds screens serializer verilog

Last synced: about 2 months ago
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An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

• Host: GitHub
• URL: https://github.com/racerxdl/lvds-7-to-1-serializer
• Owner: racerxdl
• License: mit
• Created: 2013-11-23T03:03:12.000Z (about 11 years ago)
• Default Branch: master
• Last Pushed: 2013-11-23T03:13:55.000Z (about 11 years ago)
• Last Synced: 2024-05-02T01:25:50.013Z (8 months ago)
• Topics: fpga, lcd, lvds, screens, serializer, verilog
• Language: Verilog
• Size: 109 KB
• Stars: 44
• Watchers: 5
• Forks: 11
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
LVDS-7-to-1-Serializer

======================

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Tested on Spartan 3A Evaluation Kit

*   Target Device: `xa3s400a-4ftg256`

*   Flip-flops used: 114

*   4 Input LUTs used: 140

*   Slices used: 127

*   DCMs used: 2

*   ODDR2 used: 4

The Serializer core is composed by `lvds_clockgen.v` and `serializer.v`. But I provided an example of how to use it with `maincore.v`, `video_lvds.v` that is both files for a Video Signal Generator to common notebook LVDS TFT Panels.