https://github.com/raineggplant/mips_pipeline_cpu
a simple MIPS CPU for the Fundamental Experiment of Digital Logic and Processor course of EE, Tsinghua University
https://github.com/raineggplant/mips_pipeline_cpu
cpu mips mips32cpu tsinghua tsinghua-university
Last synced: 2 months ago
JSON representation
a simple MIPS CPU for the Fundamental Experiment of Digital Logic and Processor course of EE, Tsinghua University
- Host: GitHub
- URL: https://github.com/raineggplant/mips_pipeline_cpu
- Owner: RainEggplant
- Created: 2019-08-05T03:31:57.000Z (about 6 years ago)
- Default Branch: master
- Last Pushed: 2019-10-16T01:34:20.000Z (almost 6 years ago)
- Last Synced: 2025-07-27T01:32:14.291Z (2 months ago)
- Topics: cpu, mips, mips32cpu, tsinghua, tsinghua-university
- Language: Verilog
- Homepage:
- Size: 1.27 MB
- Stars: 14
- Watchers: 1
- Forks: 2
- Open Issues: 0