https://github.com/rajhingar/systemverilog-based-mimo-module-verification
A comprehensive SystemVerilog UVM testbench for verifying MIMO Multiple-Input Multiple Output) communication system modules including encoder, decoder, and channel estimator components.
https://github.com/rajhingar/systemverilog-based-mimo-module-verification
hdl matlab mimo-systems signal-processing systemverilog-hdl verification vivado
Last synced: 8 months ago
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A comprehensive SystemVerilog UVM testbench for verifying MIMO Multiple-Input Multiple Output) communication system modules including encoder, decoder, and channel estimator components.
- Host: GitHub
- URL: https://github.com/rajhingar/systemverilog-based-mimo-module-verification
- Owner: rajHingar
- License: mit
- Created: 2025-08-21T05:39:02.000Z (10 months ago)
- Default Branch: main
- Last Pushed: 2025-08-21T05:41:45.000Z (10 months ago)
- Last Synced: 2025-08-21T07:35:41.316Z (10 months ago)
- Topics: hdl, matlab, mimo-systems, signal-processing, systemverilog-hdl, verification, vivado
- Homepage:
- Size: 396 KB
- Stars: 0
- Watchers: 0
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# MIMO SystemVerilog UVM Verification Environment
A comprehensive SystemVerilog UVM testbench for verifying MIMO (Multiple-Input Multiple-Output) communication system modules including encoder, decoder, and channel estimator components.
## 🚀 Features
- **Complete UVM Testbench**: Industry-standard UVM-based verification environment
- **MIMO Module Coverage**: Supports encoder, decoder, and channel estimator verification
- **Advanced Verification Techniques**:
- Constrained random stimulus generation
- Coverage-driven verification (CDV)
- Assertion-based verification (ABV)
- Reference model scoreboarding
- **MATLAB Integration**: Golden reference models for complex signal processing verification
- **Comprehensive Coverage**: Functional coverage with cross-coverage and corner case analysis
- **Configurable Architecture**: Parameterizable for different antenna configurations and algorithms
## 📁 Repository Structure
```
mimo-systemverilog-uvm/
├── rtl/ # DUT modules
│ ├── mimo_encoder.sv # MIMO encoder implementation
│ ├── mimo_decoder.sv # MIMO decoder implementation
│ └── mimo_channel_estimator.sv # Channel estimation module
├── verification/
│ ├── uvm_testbench/ # UVM testbench components
│ │ ├── mimo_uvm_pkg.sv # Main UVM package
│ │ ├── mimo_uvm_components.sv # Driver, monitor, sequencer, agent
│ │ ├── mimo_scoreboard.sv # Scoreboard with reference models
│ │ ├── mimo_coverage_env.sv # Coverage collector and environment
│ │ ├── mimo_test_lib.sv # Test library
│ │ └── mimo_interfaces_tb.sv # Interfaces and top-level testbench
│ └── matlab_reference/ # MATLAB reference models
│ └── mimo_matlab_reference.m # Golden reference implementations
├── scripts/ # Build and simulation scripts
│ ├── compile_uvm.tcl # Vivado compilation script
│ ├── run_simulation.tcl # Simulation execution script
│ └── coverage_report.tcl # Coverage analysis script
├── docs/ # Documentation
│ ├── verification_plan.md # Detailed verification plan
│ ├── coverage_report.html # Coverage analysis results
│ └── user_guide.md # User guide and tutorials
├── Makefile # Build automation
└── README.md # This file
```
## 🛠️ Prerequisites
### Tools Required
- **Xilinx Vivado** 2022.1 or later (for SystemVerilog simulation)
- **MATLAB** R2021b or later with Communications Toolbox
- **Python** 3.8+ (optional, for additional analysis scripts)
### SystemVerilog/UVM Requirements
- UVM 1.2 library
- SystemVerilog IEEE 1800-2017 support
- Assertion support (SVA)
## 🚀 Quick Start
### 1. Clone Repository
```bash
git clone https://github.com/your-username/mimo-systemverilog-uvm.git
cd mimo-systemverilog-uvm
```
### 2. Environment Setup
```bash
# Set tool paths (adjust for your installation)
export VIVADO_PATH=/tools/Xilinx/Vivado/2022.1
export MATLAB_PATH=/usr/local/MATLAB/R2021b
# Add tools to PATH
export PATH=$VIVADO_PATH/bin:$MATLAB_PATH/bin:$PATH
```
### 3. Quick Simulation
```bash
# Run default random test
make run_test TEST=mimo_random_test
# Run specific test with GUI
make run_test TEST=mimo_spatial_multiplexing_test GUI=1
# Run regression suite
make regression
```
### 4. Generate Coverage Report
```bash
make coverage_report
# View results in coverage_report.html
```
## 📝 Usage Examples
### Running Different Test Scenarios
```bash
# SISO (Single Input Single Output) test
make run_test TEST=mimo_siso_test
# MIMO spatial multiplexing test
make run_test TEST=mimo_spatial_multiplexing_test
# Channel estimation focused test
make run_test TEST=mimo_channel_estimation_test
# Error injection and corner case test
make run_test TEST=mimo_error_injection_test
# Performance/stress test
make run_test TEST=mimo_performance_test
# Comprehensive regression test
make run_test TEST=mimo_regression_test
# Coverage-driven test
make run_test TEST=mimo_coverage_test
```
### Custom Test Configuration
```systemverilog
// Example: Custom test configuration
class my_custom_test extends mimo_base_test;
virtual function void configure_test();
super.configure_test();
// Custom configuration
cfg.num_tx_antennas = 8; // 8x8 MIMO
cfg.num_rx_antennas = 8;
cfg.num_data_streams = 4; // 4 spatial streams
cfg.num_transactions = 2000; // Extended test
cfg.randomize_delays = 1; // Enable delay randomization
endfunction
virtual task main_test();
// Custom test sequence
my_custom_sequence seq = my_custom_sequence::type_id::create("seq");
seq.start(env.encoder_agent.sequencer);
endtask
endclass
```
## 🎯 Verification Features
### Constrained Random Verification
- **Smart Constraints**: Realistic MIMO scenarios with proper antenna/stream relationships
- **Weighted Randomization**: Higher probability for critical corner cases
- **Scenario Coverage**: Comprehensive coverage of MIMO modes and modulation schemes
### Functional Coverage
- **Cross-Coverage**: MIMO mode × Modulation × Detection algorithm combinations
- **Corner Cases**: Singular channel matrices, high noise conditions, pilot patterns
- **Protocol Compliance**: Interface timing, handshake protocols, error conditions
### Assertion-Based Verification
- **Interface Protocols**: Handshake validation, timing constraints
- **Functional Assertions**: Signal bounds, mathematical relationships
- **Coverage Assertions**: Temporal sequence verification
### Reference Model Integration
- **MATLAB Golden Models**: Bit-accurate reference implementations
- **Automatic Comparison**: Scoreboard-based checking with tolerance handling
- **Performance Metrics**: BER calculation, SNR estimation, condition number analysis
## 📊 Coverage Analysis
### Coverage Categories
1. **Basic Configuration Coverage**: MIMO modes, modulation schemes, detection algorithms
2. **Data Stream Coverage**: Stream count, data patterns, cross-combinations
3. **Channel Condition Coverage**: Pilot patterns, noise levels, time-varying scenarios
4. **Performance Coverage**: Error conditions, SNR ranges, channel conditioning
5. **Protocol Coverage**: Interface timing, backpressure, handshake scenarios
### Coverage Goals
- **Functional Coverage**: >95%
- **Code Coverage**: >90%
- **Assertion Coverage**: 100%
- **Cross-Coverage**: >90% for critical combinations
## 🔧 Configuration Options
### DUT Configuration
```systemverilog
// mimo_config.sv parameters
int num_tx_antennas = 4; // 1, 2, 4, 8
int num_rx_antennas = 4; // 1, 2, 4, 8
int num_data_streams = 2; // 1 to min(tx,rx)
int symbol_width = 16; // Symbol precision
int data_width = 8; // Data word width
```
### Test Configuration
```systemverilog
// Test behavior control
int num_transactions = 1000; // Test length
bit enable_assertions = 1; // Assertion checking
bit enable_coverage = 1; // Coverage collection
bit randomize_delays = 1; // Interface delay randomization
```
### Coverage Configuration
```systemverilog
// Coverage control
real coverage_target = 95.0; // Target coverage percentage
bit enable_cross_coverage = 1; // Cross-coverage collection
bit enable_corner_cases = 1; // Corner case emphasis
```
## 📈 Performance Metrics
### Verification Metrics
- **Simulation Speed**: >10K transactions/second
- **Memory Usage**: <2GB for standard test configurations
- **Coverage Convergence**: <5K random transactions for 90% coverage
- **Debug Capability**: Full waveform and transaction logging
### Quality Metrics
- **Bug Detection**: >99% for seeded bugs
- **False Positive Rate**: <1%
- **Coverage Accuracy**: Verified against manual analysis
- **Reference Model Agreement**: >99.9% for valid scenarios
## 🐛 Debugging and Troubleshooting
### Common Issues
1. **Compilation Errors**
```bash
# Check UVM library path
make check_uvm
# Verify SystemVerilog syntax
make lint
```
2. **Simulation Hangs**
```bash
# Enable debug mode
make run_test TEST=mimo_random_test DEBUG=1
# Check for assertion failures
grep "ASSERTION" simulation.log
```
3. **Coverage Issues**
```bash
# Generate detailed coverage report
make detailed_coverage
# Analyze uncovered scenarios
make coverage_analysis
```
### Debug Features
- **Transaction Logging**: Detailed transaction history
- **Waveform Generation**: VCD output for signal analysis
- **Assertion Reporting**: Comprehensive assertion status
- **Coverage Tracking**: Real-time coverage monitoring
## 🤝 Contributing
### Development Workflow
1. Fork the repository
2. Create feature branch (`git checkout -b feature/amazing-feature`)
3. Commit changes (`git commit -m 'Add amazing feature'`)
4. Push to branch (`git push origin feature/amazing-feature`)
5. Open Pull Request
### Coding Standards
- **SystemVerilog Style**: Follow IEEE 1800 best practices
- **UVM Methodology**: Adhere to UVM 1.2 guidelines
- **Documentation**: Comprehensive inline documentation
- **Testing**: All new features must include tests
### Test Requirements
- New tests must achieve >95% coverage
- Reference model validation required
- Performance impact assessment
- Regression test compatibility
## 📄 License
This project is licensed under the MIT License - see the [LICENSE](LICENSE) file for details.
## 📚 References
- **UVM 1.2 User Guide**: Accellera Systems Initiative
- **SystemVerilog IEEE 1800-2017**: IEEE Standard
- **MIMO Communication Systems**: Tse & Viswanath
- **Wireless Communications**: Goldsmith
- **Digital Communications**: Proakis & Salehi
## 🙏 Acknowledgments
- Accellera Systems Initiative for UVM methodology
- Xilinx for Vivado simulation tools
- MathWorks for MATLAB Communications Toolbox
- Open source SystemVerilog community
## 📞 Support
- **Issues**: [GitHub Issues](https://github.com/your-username/mimo-systemverilog-uvm/issues)
- **Discussions**: [GitHub Discussions](https://github.com/your-username/mimo-systemverilog-uvm/discussions)
- **Email**: mimo-verification@example.com
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