https://github.com/ranjith-dhananjaya/20ghz-integer-n-pll-in-65nm-cmos-process

Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process
https://github.com/ranjith-dhananjaya/20ghz-integer-n-pll-in-65nm-cmos-process

analog capacitor charge-pump design frquency-divider ic-design-project inductor locking pfd pll vco

Last synced: 3 months ago
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Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process

• Host: GitHub
• URL: https://github.com/ranjith-dhananjaya/20ghz-integer-n-pll-in-65nm-cmos-process
• Owner: ranjith-dhananjaya
• Created: 2022-05-05T20:07:29.000Z (about 3 years ago)
• Default Branch: main
• Last Pushed: 2022-05-05T20:21:17.000Z (about 3 years ago)
• Last Synced: 2025-01-07T10:21:48.772Z (5 months ago)
• Topics: analog, capacitor, charge-pump, design, frquency-divider, ic-design-project, inductor, locking, pfd, pll, vco
• Homepage:
• Size: 3.71 MB
• Stars: 4
• Watchers: 1
• Forks: 2
• Open Issues: 1
• Metadata Files:
  • Readme: README.md

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README

        
Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence. Achieved DC power consumption of 18mW, phase noise of –96 dBc/Hz at offset frequency of 1 MHz, output power of 3dBm. The PLL was designed to have a tuning range of 18-23 GHz & locking was demonstrated through simulation