Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
https://github.com/raquentin/clash-audio
🔊 Libraries for processing audio streams on hardware via Haskell.
https://github.com/raquentin/clash-audio
clash dsp haskell
Last synced: about 1 month ago
JSON representation
🔊 Libraries for processing audio streams on hardware via Haskell.
- Host: GitHub
- URL: https://github.com/raquentin/clash-audio
- Owner: raquentin
- License: mit
- Created: 2024-10-02T01:56:59.000Z (3 months ago)
- Default Branch: main
- Last Pushed: 2024-11-20T16:44:41.000Z (about 2 months ago)
- Last Synced: 2024-12-08T19:44:27.937Z (about 1 month ago)
- Topics: clash, dsp, haskell
- Language: Haskell
- Homepage:
- Size: 16.8 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE.md
Awesome Lists containing this project
README
# 🔊 clash-audio
An open-source IP library for processing audio streams on hardware with Haskell.
## Running The Project
### Running Tests
- `cabal run clashi`
- `clashi> :l tests/Tests/`
- `clashi> sampleN tb`
You'll want to use `sampleN` to finitely sample the output wire of the circuit. Otherwise your console will be filled with `True` until you interrupt. The output of tb is True if all specified stimuli are exhausted, not whether the tests "pass" really, since the signal holds a value indefinetly. If a test's expected output doesn't match an input, you'll see the error below:
```
cycle(): 4, outputVerifier
expected value: 9, not equal to actual value: 8
```
In this example, the expected value didn't match the actual output on clock cycle 4.
### Generating Verilog
- `cabal run clashi`
- `clashi> :l src/`
- `clashi> :verilog`
Verilog entity will be written to `/verilog/..topEntity/.v`.
### Creating AMD Xilinx Project Files
See `/examples` with constraints and Tcl files. These files generate Vivado project files to show how different cores work.
## Resources
- Getting Started with FPGAs by Russell Merrick
- Retrocomputing with Clash: Haskell for FPGA Hardware Design by Gergo Erdi
- Haskell Programming from First Principles by Christopher Allen and Julie Moronu
- Advanced Digital Design with the Verilog HDL by Michael Ciletti
- Haskell for Imperative Programmers by Philipp Hagenlocher