https://github.com/rdsik/schoolriscv
CPU microarchitecture, step by step
https://github.com/rdsik/schoolriscv
assembly makefile modelsim quartus verilog-hdl
Last synced: about 1 month ago
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CPU microarchitecture, step by step
- Host: GitHub
- URL: https://github.com/rdsik/schoolriscv
- Owner: RDSik
- License: other
- Fork: true (zhelnio/schoolRISCV)
- Created: 2024-08-05T10:01:10.000Z (over 1 year ago)
- Default Branch: 00_simple
- Last Pushed: 2024-09-09T20:35:51.000Z (about 1 year ago)
- Last Synced: 2024-09-29T05:43:30.291Z (about 1 year ago)
- Topics: assembly, makefile, modelsim, quartus, verilog-hdl
- Language: Makefile
- Homepage:
- Size: 15.3 MB
- Stars: 0
- Watchers: 0
- Forks: 0
- Open Issues: 0