https://github.com/rec0de/obdd-gen
Parses boolean logic formulas into ordered binary decision trees
https://github.com/rec0de/obdd-gen
Last synced: 8 months ago
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Parses boolean logic formulas into ordered binary decision trees
- Host: GitHub
- URL: https://github.com/rec0de/obdd-gen
- Owner: rec0de
- License: other
- Created: 2021-05-18T14:05:42.000Z (about 5 years ago)
- Default Branch: main
- Last Pushed: 2024-07-26T08:42:34.000Z (almost 2 years ago)
- Last Synced: 2025-04-11T19:46:42.106Z (about 1 year ago)
- Language: Kotlin
- Homepage:
- Size: 771 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE.md
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README
# obdd-gen
obdd-gen is a tool to generate Ordered Binary Decision Diagrams or (O)BDDs from boolean logic formulas. Additionally, obdd-gen includes an experimental tool for LUT-mapping based on QRBDDs.
## Building
To build an executable jar, run
`gradle assemble && gradle shadowJar`. The executable will be located in `build/libs/`.
## Formula Input
The boolean formula input format looks like this: `!(a -> b) & (c <=> d | e) ^ !a`. The usual associativity and precedence rules apply.
## BDD / QRBDD Generation
Builds a BDD from the given boolean formula, producing a DOT graph or JSON representation of the BDD.
```
java -jar obdd-gen.jar [flags] [formula]
Flags:
--naive Use naive BDD generation (slow, bad)
--reduce Produce fully reduced BDD
--quasireduce Produce quasi-reduced BDD
--json Output JSON rather than DOT
--out=[path] Output location, default bdd.dot/bdd.json
--order=[order] Specify variable evaluation order
none Use variables in order of appearance
weight Use variable weight heuristic
count Use variables in order of global count
subgraph Use subgraph complexity heuristic
a,b,c Use custom variable order
```
## LUT Mapping
LUT mapping maps a BLIF input file to an equivalent BLIF output that is composed only of 5-input (or smaller) look-up tables, optimizing for the smallest number of LUTs.
**Note:** The BLIF parser currently only supports a small subset of BLIF. Inputs should be plain networks of logic gates using ON-set specification. Generic latches are somewhat supported.
```
java -jar obdd-gen.jar --blif-map [flags] [input.blif]
Flags:
--lutcap=[n] Set maximum LUT input size (default 5)
--loglevel=[0-5] Set verbosity 5=silent 0=full default 4
--out=[path] Output location, default mapped.blif
```