https://github.com/red-portal/eee3163-pcfg
Sogang University EEE3163 Project, PC Function Generator
https://github.com/red-portal/eee3163-pcfg
sogang vhdl
Last synced: 3 months ago
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Sogang University EEE3163 Project, PC Function Generator
- Host: GitHub
- URL: https://github.com/red-portal/eee3163-pcfg
- Owner: Red-Portal
- Created: 2018-11-03T04:32:23.000Z (over 6 years ago)
- Default Branch: master
- Last Pushed: 2018-11-27T14:08:27.000Z (over 6 years ago)
- Last Synced: 2025-01-18T03:45:58.811Z (5 months ago)
- Topics: sogang, vhdl
- Language: VHDL
- Size: 5.29 MB
- Stars: 1
- Watchers: 4
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# EEE3163 PC Function Generator
Project of Sogang University EEE3163 Advanced Digital Circuit Design class.
Developed on a custom FPGA board with a on board ADC, DAC, and USB comm module.
## ip core
This repository does not include the ip core modules.
You need to generate the IP cores below.
### memory_block
A RAM block generated by the Xilinx memory block generator.
* Simple two-port RAM
* address 11 bits, data 8 bits
* enable a side, enable b side
### counter
A simple counter
* clock enable
* 11 bits
### load_counter
A simple counter with data load
* data load
* clock enable
* 11 bits
### accumulator
A accumulator register used in the average filter
* input 9 bits, output 19 bits
* add and substract
* clock enable
## Hierarchy
The top module is pcfg_top.vhd
All control signals are generated in control_signal_gen.vhd
Each function has its dedicated controller.
* PC mode: controller_pc.vhd
* AD mode: controller_ad.vhd
* DA mode: controller_da.vhd
* Data Transfer mode: controller_dt.vhd
* Average mode: controller_filter.vhd
## Test benches
files with the naming convention
* *_test.vhd
* tb_*.vhd
are test benches. Please exclude them from the implementation.