https://github.com/redchenjs/clock_data_recovery_max10
Clock Data Recovery | 時鐘數據恢復
https://github.com/redchenjs/clock_data_recovery_max10
bit cdr clock fpga max10 recovery
Last synced: 5 months ago
JSON representation
Clock Data Recovery | 時鐘數據恢復
- Host: GitHub
- URL: https://github.com/redchenjs/clock_data_recovery_max10
- Owner: redchenjs
- Created: 2020-08-08T12:42:03.000Z (almost 6 years ago)
- Default Branch: master
- Last Pushed: 2020-08-09T08:45:11.000Z (almost 6 years ago)
- Last Synced: 2025-07-11T02:50:25.466Z (12 months ago)
- Topics: bit, cdr, clock, fpga, max10, recovery
- Language: Verilog
- Homepage:
- Size: 16.6 KB
- Stars: 10
- Watchers: 1
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
Clock Data Recovery
===================
## Preparing
### Obtain the source
```
git clone https://github.com/redchenjs/clock_data_recovery_max10.git
```
### Update an existing repository
```
git pull
```
## Building
* Quartus Prime 20.1.0 Lite Edition