https://github.com/regymm/muzy

2-layer FPGA development board with ZYNQ 7010/7020 400-pin BGA.
https://github.com/regymm/muzy

Last synced: 11 days ago
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2-layer FPGA development board with ZYNQ 7010/7020 400-pin BGA.

• Host: GitHub
• URL: https://github.com/regymm/muzy
• Owner: regymm
• License: gpl-3.0
• Created: 2023-05-20T08:58:59.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2024-09-29T13:13:26.000Z (5 months ago)
• Last Synced: 2025-01-29T19:48:44.079Z (14 days ago)
• Size: 2.14 MB
• Stars: 19
• Watchers: 2
• Forks: 2
• Open Issues: 2
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# Muzy-2

2-layer FPGA development board with ZYNQ 7010/7020 400-pin BGA.  

Pad size was shrinked due to clearance requirements -- JLCPCB 2-layer 5 mil line width, 0.5/0.3 mm via. 

## Working

PL(FPGA fabric) JTAG & bitstream downloading, SDRAM tested up to 110 MHz, 640x480 VGA, BTN/LED, PMOD

Loading PS(ARM cores) program via JTAG in Xilinx SDK, PS UART, PS SD card, PS EMIO

## Not Working

PL SD card -- probably due to no pullup resistors! A PMOD SD card module works.

PS load bitstream from SD card -- it seems impossible due to no big enough block of memory. Either SPI flash or DDR is required. 

JTAG at 30 MHz maybe not stable

## Gallery

![](doc/muzy-2-3d.png)

Running with [self-designed JTAG/UART bridge](https://github.com/regymm/ymmcu-ft2232)

![](doc/muzy-2.jpg)