https://github.com/rejunity/zero-to-asic-wrapped-parallax
Tiny experimental ASIC design for efabless/OpenLane fab.
https://github.com/rejunity/zero-to-asic-wrapped-parallax
asic efabless fpga openlane verilog
Last synced: 3 months ago
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Tiny experimental ASIC design for efabless/OpenLane fab.
- Host: GitHub
- URL: https://github.com/rejunity/zero-to-asic-wrapped-parallax
- Owner: rejunity
- License: apache-2.0
- Created: 2021-11-10T20:58:57.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2021-11-16T16:40:11.000Z (over 3 years ago)
- Last Synced: 2025-03-15T15:54:35.852Z (4 months ago)
- Topics: asic, efabless, fpga, openlane, verilog
- Language: Verilog
- Homepage:
- Size: 1.96 MB
- Stars: 4
- Watchers: 2
- Forks: 1
- Open Issues: 0