https://github.com/rejunity/zero-to-asic-wrapped-parallax

Tiny experimental ASIC design for efabless/OpenLane fab.
https://github.com/rejunity/zero-to-asic-wrapped-parallax

asic efabless fpga openlane verilog

Last synced: about 1 month ago
JSON representation

Tiny experimental ASIC design for efabless/OpenLane fab.

• Host: GitHub
• URL: https://github.com/rejunity/zero-to-asic-wrapped-parallax
• Owner: rejunity
• License: apache-2.0
• Created: 2021-11-10T20:58:57.000Z (about 3 years ago)
• Default Branch: main
• Last Pushed: 2021-11-16T16:40:11.000Z (almost 3 years ago)
• Last Synced: 2023-03-11T13:05:08.418Z (over 1 year ago)
• Topics: asic, efabless, fpga, openlane, verilog
• Language: Verilog
• Homepage:
• Size: 1.96 MB
• Stars: 2
• Watchers: 1
• Forks: 1
• Open Issues: 0

Awesome Lists containing this project