https://github.com/rfdonnelly/lfsr-parallel
Verilog Parallel LFSR Generator
https://github.com/rfdonnelly/lfsr-parallel
crc hdl lfsr systemverilog
Last synced: 10 months ago
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Verilog Parallel LFSR Generator
- Host: GitHub
- URL: https://github.com/rfdonnelly/lfsr-parallel
- Owner: rfdonnelly
- Created: 2020-06-05T18:12:28.000Z (about 6 years ago)
- Default Branch: main
- Last Pushed: 2024-06-08T02:58:39.000Z (about 2 years ago)
- Last Synced: 2024-06-08T03:47:51.817Z (about 2 years ago)
- Topics: crc, hdl, lfsr, systemverilog
- Language: Rust
- Homepage: https://rfdonnelly.github.io/lfsr-parallel
- Size: 103 KB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.adoc
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README
# Parallel LFSR
[link=https://github.com/rfdonnelly/lfsr-parallel/actions/workflows/ci.yml]
image::https://github.com/rfdonnelly/lfsr-parallel/actions/workflows/ci.yml/badge.svg[CI]
This project generates parallel Galois LFSR implementations for calculating polynomial codes (e.g. CRC) in hardware.
Parallel implementations are derived by unrolling the serial LFSR implementation.
https://rfdonnelly.github.io/lfsr-parallel[Try me!]
## Features
* Any data word size
* Any code size
* Optional initial state
* Term reduction
## Example
Given a 32-bit data word and the following generator polynomial:
[listing]
----
g(x) = x^8 + x^2 + x^1 + x
----
With a normal representation of:
[listing]
----
0x07
----
Running:
[source,sh]
----
lfsr --data-size 32 --state-size 8 --polynomial 0x07
----
Will generate the following parallel implementation:
[listing]
----
c[0] = d[0] ^ d[6] ^ d[7] ^ d[8] ^ d[12] ^ d[14] ^ d[16] ^ d[18] ^ d[19] ^ d[21] ^ d[23] ^ d[28] ^ d[30] ^ d[31]
c[1] = d[0] ^ d[1] ^ d[6] ^ d[9] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[28] ^ d[29] ^ d[30]
c[2] = d[0] ^ d[1] ^ d[2] ^ d[6] ^ d[8] ^ d[10] ^ d[12] ^ d[13] ^ d[15] ^ d[17] ^ d[22] ^ d[24] ^ d[25] ^ d[28] ^ d[29]
c[3] = d[1] ^ d[2] ^ d[3] ^ d[7] ^ d[9] ^ d[11] ^ d[13] ^ d[14] ^ d[16] ^ d[18] ^ d[23] ^ d[25] ^ d[26] ^ d[29] ^ d[30]
c[4] = d[2] ^ d[3] ^ d[4] ^ d[8] ^ d[10] ^ d[12] ^ d[14] ^ d[15] ^ d[17] ^ d[19] ^ d[24] ^ d[26] ^ d[27] ^ d[30] ^ d[31]
c[5] = d[3] ^ d[4] ^ d[5] ^ d[9] ^ d[11] ^ d[13] ^ d[15] ^ d[16] ^ d[18] ^ d[20] ^ d[25] ^ d[27] ^ d[28] ^ d[31]
c[6] = d[4] ^ d[5] ^ d[6] ^ d[10] ^ d[12] ^ d[14] ^ d[16] ^ d[17] ^ d[19] ^ d[21] ^ d[26] ^ d[28] ^ d[29]
c[7] = d[5] ^ d[6] ^ d[7] ^ d[11] ^ d[13] ^ d[15] ^ d[17] ^ d[18] ^ d[20] ^ d[22] ^ d[27] ^ d[29] ^ d[30]
----
## Possible Future Work
* Pipelining