https://github.com/rggen/rggen

Code generation tool for configuration and status registers
https://github.com/rggen/rggen

amba apb asic axi csr eda fpga ral register-descriptions rtl soc systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl wiki-documents wishbone-bus

Last synced: about 1 month ago
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Code generation tool for configuration and status registers

• Host: GitHub
• URL: https://github.com/rggen/rggen
• Owner: rggen
• License: mit
• Created: 2019-04-10T09:41:17.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2023-12-17T14:24:40.000Z (9 months ago)
• Last Synced: 2023-12-17T15:29:54.936Z (9 months ago)
• Topics: amba, apb, asic, axi, csr, eda, fpga, ral, register-descriptions, rtl, soc, systemverilog, uvm, uvm-ral-model, uvm-register-model, verilog, vhdl, wiki-documents, wishbone-bus
• Language: Ruby
• Homepage:
• Size: 497 KB
• Stars: 257
• Watchers: 14
• Forks: 36
• Open Issues: 12
• Metadata Files:
  • Readme: README.md
  • Contributing: CONTRIBUTING.md
  • Funding: .github/FUNDING.yml
  • License: LICENSE
  • Code of conduct: CODE_OF_CONDUCT.md

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