https://github.com/richasavant/icarus-verilog-hdl-logical-circuits-2023

This repository focuses on designing and simulating logical circuits using Verilog HDL (Hardware Description Language) with the Icarus Verilog simulator.
https://github.com/richasavant/icarus-verilog-hdl-logical-circuits-2023

adders arithmetic-circuits combinational-circuit decoders demultiplexer encoders flip-flops hdl icarus-verilog logic-gates multiplexer ripple-carry-adder sequential-circuits shift-registers

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This repository focuses on designing and simulating logical circuits using Verilog HDL (Hardware Description Language) with the Icarus Verilog simulator.

• Host: GitHub
• URL: https://github.com/richasavant/icarus-verilog-hdl-logical-circuits-2023
• Owner: RichaSavant
• Created: 2024-07-13T15:41:22.000Z (5 months ago)
• Default Branch: main
• Last Pushed: 2024-07-15T16:20:03.000Z (5 months ago)
• Last Synced: 2024-07-15T19:50:05.250Z (5 months ago)
• Topics: adders, arithmetic-circuits, combinational-circuit, decoders, demultiplexer, encoders, flip-flops, hdl, icarus-verilog, logic-gates, multiplexer, ripple-carry-adder, sequential-circuits, shift-registers
• Language: Verilog
• Homepage:
• Size: 76.2 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
This repository focuses on designing and simulating logical circuits using Verilog HDL (Hardware Description Language) with the Icarus Verilog simulator. This project aims to provide a collection of Verilog code examples and testbenches for various logical circuits, facilitating learning and experimentation in digital design and HDL programming.

### Key Features and Contents:

1. **Basic Logic Gates**:

   - Verilog code for basic logic gates such as AND, OR, NOT, NAND, NOR, XOR, and XNOR.

   - Testbenches to verify the functionality of each gate through simulation.

2. **Combinational Circuits**:

   - Implementation of combinational logic circuits including multiplexers, demultiplexers, encoders, decoders, and adders (half and full adders).

   - Simulation files to test and validate the behavior of these circuits.

3. **Sequential Circuits**:

   - Verilog designs for sequential circuits like flip-flops (SR, D, JK, T) and latches.

   - Testbenches to simulate clock-driven operations and state changes in sequential circuits.

4. **Arithmetic Circuits**:

   - Code for arithmetic circuits such as ripple carry adders, subtractors, multipliers, and dividers.

   - Test cases to ensure accurate arithmetic operations and handling of carry/borrow bits.

5. **Shift Registers and Counters**:

   - Implementation of various types of shift registers (serial-in serial-out, serial-in parallel-out, etc.).

   - Design of different counters (binary, BCD, up/down) with corresponding simulation files.

### Objective and Impact:

The primary objective of this repository is to enhance understanding of digital circuits and the practical application of HDL in circuit design and simulation. It also provides a strong foundation for more advanced digital design projects and encourages the exploration of complex digital systems using Verilog HDL.