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https://github.com/ridecore/ridecore
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
https://github.com/ridecore/ridecore
Last synced: 2 months ago
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RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
- Host: GitHub
- URL: https://github.com/ridecore/ridecore
- Owner: ridecore
- License: other
- Created: 2016-03-29T05:51:08.000Z (almost 9 years ago)
- Default Branch: master
- Last Pushed: 2017-07-12T12:04:03.000Z (over 7 years ago)
- Last Synced: 2024-08-03T01:39:44.647Z (6 months ago)
- Language: Verilog
- Homepage:
- Size: 725 KB
- Stars: 307
- Watchers: 34
- Forks: 62
- Open Issues: 2