https://github.com/riscv/riscv-aia

https://github.com/riscv/riscv-aia

Last synced: about 2 months ago
JSON representation

• Host: GitHub
• URL: https://github.com/riscv/riscv-aia
• Owner: riscv
• License: cc-by-4.0
• Created: 2021-05-24T15:30:04.000Z (over 3 years ago)
• Default Branch: main
• Last Pushed: 2024-11-13T18:20:44.000Z (2 months ago)
• Last Synced: 2024-11-13T19:26:31.211Z (2 months ago)
• Language: Makefile
• Homepage: https://jira.riscv.org/browse/RVG-59
• Size: 6.19 MB
• Stars: 80
• Watchers: 27
• Forks: 19
• Open Issues: 31
• Metadata Files:
  • Readme: README.adoc
  • License: LICENSE

Awesome Lists containing this project

README

        
= RISC-V Advanced Interrupt Architecture (AIA)

The RISC-V Advanced Interrupt Architecture (AIA) builds upon the

interrupt-handling functionality of the basic RISC-V ISA to add support

mainly for the following:

* Message-signaled interrupts (MSIs) from devices.

* Direct control of device interrupts (as MSIs) by a guest operating

system running in virtual supervisor mode (VS mode), reducing the

reliance on regular hypervisor intervention.

* Additional standard local interrupts for RISC-V harts.

* Intermixing of priorities of local interrupts and device (external)

interrupts.

* Conditional delegation of local interrupts to lower privilege levels,

including to virtual machines.

== Obtaining the document

A pre-built PDF is usually available under Releases:

https://github.com/riscv/riscv-aia/releases

== Licensing

The files in this repository are licensed under the Creative Commons

Attribution 4.0 International License (CC-BY 4.0).

The full license text is available at

https://creativecommons.org/licenses/by/4.0/.