https://github.com/riscv-non-isa/riscv-elf-psabi-doc

A RISC-V ELF psABI Document
https://github.com/riscv-non-isa/riscv-elf-psabi-doc

Last synced: about 2 months ago
JSON representation

A RISC-V ELF psABI Document

• Host: GitHub
• URL: https://github.com/riscv-non-isa/riscv-elf-psabi-doc
• Owner: riscv-non-isa
• License: cc-by-4.0
• Created: 2016-11-03T19:12:02.000Z (almost 8 years ago)
• Default Branch: master
• Last Pushed: 2024-07-23T13:22:35.000Z (2 months ago)
• Last Synced: 2024-07-23T15:33:11.636Z (2 months ago)
• Language: Python
• Homepage: https://jira.riscv.org/browse/RVG-4
• Size: 9.06 MB
• Stars: 665
• Watchers: 72
• Forks: 158
• Open Issues: 81
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

        
# RISC-V ELF psABI Document

Processor-specific application binary interface document for RISC-V.

This document includes the following items:

- Procedure Calling Convention

- ELF Object Files Format

- DWARF Debug Information Format

- Code Model

- Relocation

- Relaxation

The AsciiDoc sources can be rendered by GitHub, and pre-built PDFs can be downloaded from the repository's [releases](https://github.com/riscv/riscv-elf-psabi-doc/releases).

# Navigation

----------------------------------------------------------------------------------------------------------

Name                                | URL                                                   | Description

------------------------------------|-------------------------------------------------------|--------------

RISC-V ELF psABI                    | https://github.com/riscv-non-isa/riscv-elf-psabi-doc  | Processor-specific application binary interface document.

RISC-V Embedded ABI (Draft)         | https://github.com/riscv-non-isa/riscv-eabi-spec      | Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.

RISC-V C API                        | https://github.com/riscv-non-isa/riscv-c-api-doc      | RISC-V-specific predefined macros, function attributes and language extensions.

RISC-V Assembly Programmer's Manual | https://github.com/riscv-non-isa/riscv-asm-manual     | Document for pseudoinstructions and assembly directives.

RISC-V Toolchain Conventions        | https://github.com/riscv-non-isa/riscv-toolchain-conventions  | RISC-V-specific toolchain behavior and command line option.

RISC-V Semihosting Spec             | https://github.com/riscv/riscv-semihosting-spec       | Spec for semihosting.

RISC-V Supervisor Binary Interface  | https://github.com/riscv-non-isa/riscv-sbi-doc        | Spec for SBI.

# Links

[Policy for Merging Pull Requests](policy.md)