https://github.com/riscv-steel/riscv-steel

Free and open collection of RISC-V IP.
https://github.com/riscv-steel/riscv-steel

core cores embedded-systems ip processors risc-v riscv rv32i systems-on-chip-design uart zicsr

Last synced: about 3 hours ago
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Free and open collection of RISC-V IP.

• Host: GitHub
• URL: https://github.com/riscv-steel/riscv-steel
• Owner: riscv-steel
• License: mit
• Created: 2020-05-03T19:29:10.000Z (over 4 years ago)
• Default Branch: main
• Last Pushed: 2024-04-30T23:05:00.000Z (6 months ago)
• Last Synced: 2024-05-08T02:16:47.362Z (6 months ago)
• Topics: core, cores, embedded-systems, ip, processors, risc-v, riscv, rv32i, systems-on-chip-design, uart, zicsr
• Language: Verilog
• Homepage: https://riscv-steel.github.io/riscv-steel/
• Size: 190 MB
• Stars: 110
• Watchers: 12
• Forks: 17
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • Contributing: CONTRIBUTING.md
  • Funding: FUNDING.yml
  • License: LICENSE
  • Authors: AUTHORS.md

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README

        
RISC-V Steel


RISC-V Steel is a microcontroller design developed in Verilog that implements the RV32I instruction set of RISC-V. It is designed for easy, seamless integration into embedded systems, systems-on-chip (SoC), and FPGA designs, facilitating the rapid development of innovative RISC-V applications.

RISC-V Steel can run real-time operating systems such as FreeRTOS, as well as bare-metal embedded software. Its design includes components such as memory, timers, and interfaces for UART, GPIO, and SPI communication, enabling RISC-V Steel to integrate with a variety of sensors and actuators commonly used in embedded applications.

Check out [RISC-V Steel Documentation][1].

## Get Started

The quickest way to get started is to implement one of the example projects on your FPGA. Check it out:

- [Hello World Example][2]

- [FreeRTOS Example][3]

See the [User Guide][4] to learn how to create your own applications.

## License

RISC-V Steel is distributed under the [MIT License][5].

## Need help?

Please open a [new issue][6].

[1]: https://riscv-steel.github.io/riscv-steel

[2]: https://riscv-steel.github.io/riscv-steel/examples/helloworld

[3]: https://riscv-steel.github.io/riscv-steel/examples/freertos

[4]: https://riscv-steel.github.io/riscv-steel/userguide/

[5]: LICENSE

[6]: https://github.com/riscv-steel/riscv-steel/issues