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https://github.com/riscvarchive/riscv-svadu

The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.
https://github.com/riscvarchive/riscv-svadu

Last synced: 11 days ago
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The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.

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README

        

[NOTE]
====
Hardware Updating of PTE A/D Bits (Svadu) has been merged into the Privileged Specification. Please log any issues against the link:https://github.com/riscv/riscv-isa-manual[RISC-V ISA Manual] repository.
====

= RISC-V Hardware Updating of PTE A/D Bits

The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.

= License

This work is licensed under a Creative Commons Attribution 4.0 International License (CC-BY-4.0).
See the link:LICENSE[LICENSE] file for details.

= Contributors

Contributors to this specification are contained in the link:contributors.adoc[contributors] file.

For instructions on how to contribute please see the link:CONTRIBUTING.md[CONTRIBUTING] file.

= Dependencies

To build the document, you'll need the following tools installed on your system:

```
Make
asciiDoctor-pdf, asciidoctor-bibtex, asciidoctor-diagram and asciidoctor-mathematical
Docker
```

= Cloning and Building the Document

This project uses submodules to include the RISC-V documentation toolchain.

```
git clone --recurse-submodule https://github.com/riscv/riscv-svadu.git
cd ./riscv-svadu.git
make VERSION=v1.0.0 REVMARK=Draft
```

`VERSION`: Represents the version of the specification being built. By default, this is set to 'v0.0.0'. You can change this to a different value, like 'v1.0.0', 'v1.1.0', etc., based on the current version of your specification.

`REVMARK`: This represents a revision marker for the project. Its default value is 'Draft'. You may want to change this to something like 'Release', 'Stable' or 'Ratified'.