https://github.com/risto97/svuvm-socmake
SystemVerilog UVM SoCMake package
https://github.com/risto97/svuvm-socmake
Last synced: 7 months ago
JSON representation
SystemVerilog UVM SoCMake package
- Host: GitHub
- URL: https://github.com/risto97/svuvm-socmake
- Owner: Risto97
- Created: 2024-10-10T18:56:47.000Z (about 1 year ago)
- Default Branch: master
- Last Pushed: 2025-02-08T22:21:50.000Z (8 months ago)
- Last Synced: 2025-02-08T23:23:12.360Z (8 months ago)
- Language: CMake
- Size: 31.3 KB
- Stars: 0
- Watchers: 1
- Forks: 1
- Open Issues: 0
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Metadata Files: