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https://github.com/riyasach189/rfdc_loopback_on_rfsoc4x2
The aim of this project is to demonstrate the working of the RF Data Converter IP by analyzing and replicating a part of the official Xilinx design. The goal is to recreate the radio hierarchy using custom IPs (amplitude controller and packet generator) designed in Vitis HLS 2022.1.
https://github.com/riyasach189/rfdc_loopback_on_rfsoc4x2
adc dac jupyter-notebook pynq rfdc rfsoc4x2 vitis vitis-hls vivado-hls
Last synced: 7 days ago
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The aim of this project is to demonstrate the working of the RF Data Converter IP by analyzing and replicating a part of the official Xilinx design. The goal is to recreate the radio hierarchy using custom IPs (amplitude controller and packet generator) designed in Vitis HLS 2022.1.
- Host: GitHub
- URL: https://github.com/riyasach189/rfdc_loopback_on_rfsoc4x2
- Owner: riyasach189
- Created: 2024-08-11T11:27:42.000Z (3 months ago)
- Default Branch: master
- Last Pushed: 2024-08-11T12:21:57.000Z (3 months ago)
- Last Synced: 2024-08-12T12:39:36.612Z (3 months ago)
- Topics: adc, dac, jupyter-notebook, pynq, rfdc, rfsoc4x2, vitis, vitis-hls, vivado-hls
- Language: TeX
- Homepage:
- Size: 412 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md