https://github.com/riyasach189/vitis_hls_2022.1_examples

This is a collection of some examples designed in the Vivado Design Suite.
https://github.com/riyasach189/vitis_hls_2022.1_examples

amd axi-lite axi-stream hls jupyter pynq pynq-z2 rfsoc4x2 vivado xilinx

Last synced: 2 months ago
JSON representation

This is a collection of some examples designed in the Vivado Design Suite.

• Host: GitHub
• URL: https://github.com/riyasach189/vitis_hls_2022.1_examples
• Owner: riyasach189
• Created: 2024-06-22T09:53:16.000Z (6 months ago)
• Default Branch: main
• Last Pushed: 2024-06-24T07:28:07.000Z (6 months ago)
• Last Synced: 2024-10-11T14:42:30.930Z (2 months ago)
• Topics: amd, axi-lite, axi-stream, hls, jupyter, pynq, pynq-z2, rfsoc4x2, vivado, xilinx
• Language: Tcl
• Homepage:
• Size: 1.18 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

        
# Table of Contents

| Serial No. | Name                        | Description                                         | Vivado and HLS Version | Board     |

|------------|-----------------------------|-----------------------------------------------------|------------------------|-----------|

| 1          | Simple Arithmetic Calculation | Fixed point data transfer using AXI Lite interface  | 2019.1                 | PYNQ Z2   |

| 2          | Matrix Multiplication       | Floating point data transfer using AXI Stream interface | 2019.1                 | PYNQ Z2   |

| 3          | Simple Arithmetic Calculation | Fixed point data transfer using AXI Lite interface  | 2022.1                 | RFSoC4x2   |

| 4          | Matrix Multiplication       | Floating point data transfer using AXI Stream interface | 2022.1                 | PYNQ Z2   |

| 5          | Addition 1 (Add 5 to Input) | Fixed point data transfer using AXI Stream interface | 2022.1                   | PYNQ Z2   |

| 6          | Addition 1 (Add 5 to Input) | Fixed point data transfer using AXI Stream interface  | 2022.1                 | RFSoC4x2  |

| 7          | Simple Arithmetic Calculation | Floating point data transfer using AXI Lite interface | 2022.1                 | RFSoC4x2  |

| 8          | Matrix Multiplication       | Floating point data transfer using AXI Stream interface | 2022.1                 | RFSoC4x2  |

| 9          | Addition 2 (Add 2 Numbers)  | Floating point data transfer using AXI Stream interface | 2022.1                 | RFSoC4x2   |

| 10         | Addition 3  (Add 0.5 to Input)  | Floating point data transfer using AXI Stream interface | 2022.1                 | RFSoC4x2  |

| 11         | Aggregation                 | Using aggregate pragma                               | 2022.1                 | RFSoC4x2  |

# Sources

[Algorithms to Architure Lab IIITD](https://youtu.be/Nj6JRQzwpwk?feature=shared)

[HLS Stream IP with DMA Tutorial](https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-part-3-using-the-hls-ip-from-pynq/3346)

[PYNQ Documentation](https://pynq.readthedocs.io/en/v3.0.0/_modules/index.html)

[Using DMA with PYNQ](https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133)

[Floating Point Data Transfer using AXI Stream Interface](https://pp4fpgas.readthedocs.io/en/latest/axidma2.html)

[Aggregate Pragma Examples](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Interface/Aggregation_Disaggregation)

[Aggregate Pragma Documentation](https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-aggregate)