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https://github.com/rj45/rjsc5
rjsc5 a 16-bit RISC-V CPU
https://github.com/rj45/rjsc5
cocotb cpu risc-v verilog
Last synced: 7 days ago
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rjsc5 a 16-bit RISC-V CPU
- Host: GitHub
- URL: https://github.com/rj45/rjsc5
- Owner: rj45
- License: mit
- Created: 2022-09-06T19:18:23.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2024-12-29T16:48:27.000Z (10 days ago)
- Last Synced: 2024-12-29T17:33:46.930Z (10 days ago)
- Topics: cocotb, cpu, risc-v, verilog
- Language: Assembly
- Homepage:
- Size: 1.46 MB
- Stars: 3
- Watchers: 2
- Forks: 0
- Open Issues: 2
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# rjsc5
rjsc5 (reesk-five) is a 16-bit RISC-V CPU. Because 32 bits is already done many times.
## Goal
Build a 16-bit RISC-V CPU that's feasible to build out of discrete wire chips (74xxx series ICs), though this specific project is to build it in an FPGA with verilog.
## Build Log
You can read my [build log here](buildlog/README.md).
## Specs
* RV32I
* 32-bit registers
* 16-bit ALU and data paths
* Pipelined (4? stages)
* Memory
* Harvard Architecture
* 16 bit data bus on both I & D memory ports
* Both memory ports:
* Can stall the cpu (supporting slow memory/IO)
* Can be tied to the same bus with a bus arbiter (Von Neumann Architecture)
### Stretch Goals
* Virtual Block Interface inspired virtual memory
* Unix-like OS built in Rust
* Retro graphics through a Video Display Processor
* Retro sounding audio
* M extension
* C extension
### Testing
Install [cocotb](https://github.com/cocotb/cocotb), then:
```sh
make
```
If you want to use verilator:
```sh
make SIM=verilator
```
If you want to see the VCD in gtkwave:
```sh
gtkwave rjsc5.sv
```
## Copyright
Copyright (c) 2022 github.com/rj45. All Rights Reserved.
See [LICENSE](./LICENSE) for more info.