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https://github.com/rlee287/axis_ascon
An AXI-Stream Ascon core
https://github.com/rlee287/axis_ascon
Last synced: 2 days ago
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An AXI-Stream Ascon core
- Host: GitHub
- URL: https://github.com/rlee287/axis_ascon
- Owner: rlee287
- License: mit
- Created: 2020-04-14T02:23:33.000Z (over 4 years ago)
- Default Branch: master
- Last Pushed: 2020-05-20T06:01:45.000Z (over 4 years ago)
- Last Synced: 2024-12-24T01:15:12.833Z (11 days ago)
- Language: VHDL
- Size: 21.5 KB
- Stars: 0
- Watchers: 3
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# axis-ascon
An AXI-Stream Ascon core configured over AXI-Lite
AXI-Lite register layout:
```
+-------+----+---------+
|Name |Mode|Range |
+=======+====+---------+
|Key | rw |0x00-0x0f|
|Nonce | rw |0x10-0x1f|
|Mode | rw |0x20 |
|Status | r- |0x24 |
+-------+----+---------+
```
* Key: The 128-bit key of ASCON-128
* Nonce: The 128-bit nonce of ASCON-128
Mode register detail:
```
+----------------------+-----+-----+
| Unused | AD? | E/D |
+----------------------+-----+-----+
^ ^ ^
| | |
31 1 0
```
* AD?: 1 if associated data is included, 0 otherwise
* E/D: 1 if decryption is happening, 0 if encryption is happening
Status register detail:
```
+----------------+--------+--------+
| Unused | State | Valid |
+----------------+--------+--------+
^ ^ ^
| | |
31 15 7
```
* State:
* Idle = 0
* Initialization = 1
* Associated data = 2
* Plaintext/Ciphertext = 3
* Finalization = 4
* Valid: 0 if decryption was valid and 1 if it was invalid