https://github.com/rogerfan48/hdl-fpcat

Sophomore (2024 Fall) Hardware Design Lab - Final Project - FPCAT - inspired by Battle Cat and developed using Verilog on Vivado with mouse input and VGA output
https://github.com/rogerfan48/hdl-fpcat

verilog vga vivado

Last synced: 3 months ago
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Sophomore (2024 Fall) Hardware Design Lab - Final Project - FPCAT - inspired by Battle Cat and developed using Verilog on Vivado with mouse input and VGA output

• Host: GitHub
• URL: https://github.com/rogerfan48/hdl-fpcat
• Owner: rogerfan48
• Created: 2024-12-30T06:09:02.000Z (9 months ago)
• Default Branch: main
• Last Pushed: 2025-06-17T13:17:55.000Z (4 months ago)
• Last Synced: 2025-06-17T14:27:22.423Z (4 months ago)
• Topics: verilog, vga, vivado
• Language: Verilog
• Homepage: https://github.com/rogerfan48/Project-Soph1-HDL-FPCAT/blob/main/Docs/Report.pdf
• Size: 143 MB
• Stars: 2
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# Sophomore (2024 Fall) Hardware Design Lab

## Final Project - FPCAT

- a game inspired by Battle Cat and developed by us using Verilog (some SystemVerilog) on Vivado with mouse input and VGA output.

- **Please check the report below for all implemented details.**

### Project Deliverables

- Final Project **Report**: ❗️❗️[Report.pdf](Docs/Report.pdf)❗️❗️

- Project Demonstration Video: [YouTube Video Link](https://www.youtube.com/watch?v=rUI0usMOb2s)

- Gameplay Screenshot:

![FPCAT](https://github.com/user-attachments/assets/eec938d6-4ab3-4b99-85c6-222887b89268)

![CleanShot 2025-06-17 at 21 17 07@2x](https://github.com/user-attachments/assets/a68f2bd7-2fac-492f-be70-58570acfaa6e)

### Others

- For my HDL coursework, including all my exercises, assignments, and laboratory work, please refer to this repo: [HDL-Course](https://github.com/rogerfan48/HDL-Course)