https://github.com/roscibely/arithmetic-logic-unit

A simple arithmetic logic unit (ALU) with System verilog
https://github.com/roscibely/arithmetic-logic-unit

alu arithmetic verilog vhdl

Last synced: 7 months ago
JSON representation

A simple arithmetic logic unit (ALU) with System verilog

• Host: GitHub
• URL: https://github.com/roscibely/arithmetic-logic-unit
• Owner: roscibely
• Created: 2020-08-21T18:40:08.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2020-08-21T22:09:00.000Z (about 5 years ago)
• Last Synced: 2025-01-21T21:47:14.466Z (9 months ago)
• Topics: alu, arithmetic, verilog, vhdl
• Language: SystemVerilog
• Homepage:
• Size: 84 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

          
# Arithmetic Logic Unit

 1. Hardware implementation in system verilog of a simple arithmetic logic unit (ALU) of 6 bits and 16 operations

![Figure](https://github.com/roscibely/arithmetic-logic-unit/blob/master/ula.jpg)

• Inputs: Operating A (6bits), Operating B (6bits), Reset, Clock, Mode Selection (Arithmetic or Logical), Operation Selection (3bits).

• Outputs: Output ALU (6bits), Carryout, Zero

The ALU outlined in the block diagram has two input operands (operands A and B) of 6 bits each. In addition, the ALU also has input signals Reset, Clock, Operation Selection and Mode. The Reset signal clears all ALU outputs. The Clock signal sets the clock of the ALU. The Mode Selection signal indicates whether the ALU will perform a logical operation or whether to perform an arithmetic operation.

The ALU uses the notation two's complement which is the most commonly used to represent signed numbers on computers. As the operands input contains 6 bits, it will be possible to represent 2^6 = 64 numbers (negative and positive).