https://github.com/roscibely/arithmetic-logic-unit

A simple arithmetic logic unit (ALU) with System verilog
https://github.com/roscibely/arithmetic-logic-unit

alu arithmetic verilog vhdl

Last synced: about 2 months ago
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A simple arithmetic logic unit (ALU) with System verilog

• Host: GitHub
• URL: https://github.com/roscibely/arithmetic-logic-unit
• Owner: roscibely
• Created: 2020-08-21T18:40:08.000Z (over 4 years ago)
• Default Branch: master
• Last Pushed: 2020-08-21T22:09:00.000Z (over 4 years ago)
• Last Synced: 2023-03-08T18:47:12.644Z (almost 2 years ago)
• Topics: alu, arithmetic, verilog, vhdl
• Language: SystemVerilog
• Homepage:
• Size: 84 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0

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