https://github.com/roscibely/sap1-computer
Model of a microprocessor
https://github.com/roscibely/sap1-computer
Last synced: 7 months ago
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Model of a microprocessor
- Host: GitHub
- URL: https://github.com/roscibely/sap1-computer
- Owner: roscibely
- Created: 2020-08-21T22:12:10.000Z (about 5 years ago)
- Default Branch: master
- Last Pushed: 2020-08-22T21:32:03.000Z (about 5 years ago)
- Last Synced: 2025-01-21T21:47:14.213Z (9 months ago)
- Language: SystemVerilog
- Size: 6.84 KB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# SAP 1 Computer
Model of a microprocessor
The SAP computer (Simple-As-Possible) was designed with the objective of presenting in a playful way the operational structure of a modern electronic computer, so that it becomes simpler to abstract the design used in computers most modern electronics.
# Project specification
The SAP architecture consists of 10 modules and one bus:
• PC (program counter) with inputs Cp, clock, reset, Ep;
• Input and MAR (Memory Address Register) with inputs LM, clock;
• RAM (Random Access Memory) with CE input and the address that comes from REM;
• IR (Instruction register) with LI, clock, reset, EI inputs;
• Accumulator with LA, clock and reset inputs;
• Adder / Subtractor with SU and EU inputs;
• Register B that has LB and clock inputs;
• Output recorder with Lo and clock inputs;
• Controller, which has as inputs clock, reset and the instruction that comes from the IR.