https://github.com/rpigor/tpsim
TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities
https://github.com/rpigor/tpsim
eda power-analysis simulator timing-analysis verilog
Last synced: 11 months ago
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TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities
- Host: GitHub
- URL: https://github.com/rpigor/tpsim
- Owner: rpigor
- License: mit
- Created: 2024-07-25T18:05:14.000Z (almost 2 years ago)
- Default Branch: master
- Last Pushed: 2024-10-18T07:00:55.000Z (over 1 year ago)
- Last Synced: 2025-01-06T02:24:08.793Z (over 1 year ago)
- Topics: eda, power-analysis, simulator, timing-analysis, verilog
- Language: C++
- Homepage:
- Size: 133 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# TPSim
**TPSim** (Timing and Power Simulator) is a gate-level simulator with timing and power estimation capabilities. It receives a combinatorial Verilog netlist as input and simulates the circuit in an event-driven fashion, using pre-characterized look-up tables to estimate events' delay, energy, and other parameters.
## Build
### Dependencies
This project mainly depends on Boost (>= 1.80.0). The Verilog parser depends on Flex and Bison. The project also uses Catch2 as the testing framework. On Ubuntu, these libraries can be installed through the following command:
```sh
sudo apt install libboost-all-dev flex bison
```
### Steps
1. Navigate to the project folder
```sh
cd TPSim
```
2. Invoke CMake to create the build directory and generate Makefiles
```sh
cmake -S . -B build
```
3. Invoke CMake to build the project
```sh
cmake --build build
```
## Run
Usage:
```sh
./tpsim -s -l [options]
```
Use the flag `--help` or `-h` to display all the options.
Tests can be executed through `ctest` or the compiled binary `./test`.