https://github.com/rustsbi/sifive-core

Low level access to SiFive RISC-V processor cores
https://github.com/rustsbi/sifive-core

Last synced: 3 days ago
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Low level access to SiFive RISC-V processor cores

• Host: GitHub
• URL: https://github.com/rustsbi/sifive-core
• Owner: rustsbi
• License: other
• Created: 2021-12-02T04:29:00.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2023-10-01T07:00:10.000Z (about 1 year ago)
• Last Synced: 2024-10-31T11:51:45.987Z (14 days ago)
• Language: Rust
• Size: 21.5 KB
• Stars: 5
• Watchers: 2
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • Changelog: CHANGELOG.md
  • License: LICENSE

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README

        
# SiFive-Core

Low level access to SiFive processor cores.

MSRV of this crate is 1.59.0. Before that version is stabilized, you may need to build under nightly newer than 2021-12-15.