https://github.com/saifalomari99/fpga_projects_saifalomari

This Repository is to showcase Saif Alomari's FPGA projects. Includes 25 high-level FPGA projects in various HDLs.
https://github.com/saifalomari99/fpga_projects_saifalomari

fpga systemverilog verilog

Last synced: 12 days ago
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This Repository is to showcase Saif Alomari's FPGA projects. Includes 25 high-level FPGA projects in various HDLs.

• Host: GitHub
• URL: https://github.com/saifalomari99/fpga_projects_saifalomari
• Owner: saifalomari99
• Created: 2024-02-22T03:40:21.000Z (11 months ago)
• Default Branch: main
• Last Pushed: 2024-05-11T20:08:02.000Z (8 months ago)
• Last Synced: 2024-11-07T15:15:35.445Z (2 months ago)
• Topics: fpga, systemverilog, verilog
• Language: SystemVerilog
• Homepage:
• Size: 78.2 MB
• Stars: 0
• Watchers: 1
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# FPGA_Projects

This Repository is to showcase Saif Alomari's FPGA projects

- Saif Alomari

- B.S. in Computer Engineering 

- Los Angeles, California

In this Repository, there is a collection of high-level projects: 

- SystemVerilog (2024):

    - 1- Barrel Shifter

    - 2- Programmable Square Wave Generator

    - 3- Early Denouncer Circuit

    - 4- ROM-based-temperature-conversion

    - 5- FIFO Buffer

    - 6- SoC_Chasing_LED_Function

    - 7- SoC_Blinking_LED_Core

    - 8- SoC_ADC_Chasing_LED_Function

    - 9- SoC_PWM_Spectrum_Display_Function

    - 10- SoC_Tapping Detection_Function

    - 11- SoC_Pmod_Rotary_Encoder_Control

    - 12- SoC_Keyboard_Chasing_LED_Function

    - 13- Vga Demo Square Generator

    - 14- SoC_Final_Project_Dynamic_Game

- Verilog (2023):

    - 1- Full Adder

    - 2- 7segments Display

    - 3- Counter using 7segments display

    - 4- Persistence_of_Vision_Project

    - 5- Digital Clock

    - 6- Sound Generator

    - 7- Alarm Clock

    - 8- FSM Debouncing Circuit

    - 9- FSMD Bit Counting Circuit

    - 10- Data Transmission

    - 11- FSM Questions Game

The SystemVerilog Projects and files in this repository are based on the excellent text by Pong Chu FPGA Prototyping by SystemVerilog Examples (Xilinx MicroBlaze MCS SoC Edition). 

The projects in this Repository were implemented on the ”Nexys A7-100T” FPGA trainer board by DIGILENT (previously known as the Nexys 4 DDR).

Part Number: xc7a100tcsg324-1

IDE: Xilinx's Vivado Design Suite