https://github.com/saisenko/mephisto

An IDE for learning RISC-V ISA
https://github.com/saisenko/mephisto

assembly cisc risc-v vliw

Last synced: 28 days ago
JSON representation

An IDE for learning RISC-V ISA

• Host: GitHub
• URL: https://github.com/saisenko/mephisto
• Owner: saisenko
• License: gpl-3.0
• Created: 2024-12-27T17:49:03.000Z (about 2 months ago)
• Default Branch: main
• Last Pushed: 2024-12-31T13:36:50.000Z (about 2 months ago)
• Last Synced: 2025-01-17T06:07:57.175Z (28 days ago)
• Language: CMake
• Size: 2.48 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

        
# Mephisto 🌌

### An Interactive IDE for Learning RISC-V Architecture

---

**Mephisto** is an innovative, user-friendly IDE designed to unlock the mysteries of modern processor architectures. Created with a learning-first approach, Mephisto helps enthusiasts, students, and engineers dive deep into **RISC** architecture through hands-on exploration and interactive tools.

## Why Mephisto?

Processor architectures drive the tech world, but mastering them can feel like taming a storm! Mephisto is here to make that journey intuitive, engaging, and fun by starting with RISC (with plans on expanding to CISC and VLIW). With a sleek interface, real-time feedback, and detailed instruction breakdowns, Mephisto aims to be your go-to learning platform for low-level architecture.

---

## Features 🌟

- **Code Editor for RISC-V Assembly**

  Write and edit RISC-V assembly code directly in the built-in editor. Execute RISC-V assembly instructions and update the state of registers and memory in real-time.

- **Register Display**

  View the contents of all 32 registers in a structured, tabular format. Registers are grouped for easy visualization (x0-x7, x8-x15, etc.).

- **Memory Viewer**

  Displays memory contents in binary format alongside their corresponding addresses. Addresses are displayed in hexadecimal for clarity.

- **Execution Status**

  Provides feedback on the execution status (e.g., "Program executed successfully").

- **Clean and Intuitive UI**

  User-friendly interface designed for simplicity and focus on learning and debugging RISC-V code. Segregated areas for editing code, viewing register states, inspecting memory, and monitoring program execution.

---

## Roadmap 🛤️

- **Current:** Implementing full RISC support (registers, memory, and instruction set)

- **Next:** Expand GUI to support detailed RISC instruction displays, debugging and error/warning highlighting

- **Future:** Add built-in tutorials and challenges, user configuration options, and a code editor