https://github.com/sajattack/redip-sid-i2s
Initial bringup experiments for I2S on the redip-sid FPGA board
https://github.com/sajattack/redip-sid-i2s
Last synced: 6 months ago
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Initial bringup experiments for I2S on the redip-sid FPGA board
- Host: GitHub
- URL: https://github.com/sajattack/redip-sid-i2s
- Owner: sajattack
- Created: 2021-08-17T06:03:22.000Z (almost 5 years ago)
- Default Branch: master
- Last Pushed: 2021-08-17T15:32:44.000Z (almost 5 years ago)
- Last Synced: 2025-03-25T05:33:30.201Z (over 1 year ago)
- Language: Verilog
- Size: 769 KB
- Stars: 0
- Watchers: 2
- Forks: 1
- Open Issues: 0
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Metadata Files: