https://github.com/samiyaalizaidi/fifo-in-verilog

Implementation of a FIFO structure for Digital Systems | Written in Verilog HDL
https://github.com/samiyaalizaidi/fifo-in-verilog

digital-system-design fifo-buffer fifo-queue verilog-hdl vivado

Last synced: about 2 months ago
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Implementation of a FIFO structure for Digital Systems | Written in Verilog HDL

• Host: GitHub
• URL: https://github.com/samiyaalizaidi/fifo-in-verilog
• Owner: samiyaalizaidi
• Created: 2024-03-11T12:47:16.000Z (10 months ago)
• Default Branch: main
• Last Pushed: 2024-03-26T16:58:14.000Z (9 months ago)
• Last Synced: 2024-10-27T22:37:28.489Z (2 months ago)
• Topics: digital-system-design, fifo-buffer, fifo-queue, verilog-hdl, vivado
• Language: Verilog
• Homepage:
• Size: 9.77 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Implementation of a FIFO Using Verilog HDL

## Parameters

 - Length of a single word: 8 bits.

 - Height of the FIFO: 32

### Input Signals

- Clock @ 1 MHz: 1 bit

- Reset: 1-bit signal to set everything to zero.

- Input Data: 8 bits

- Write: 1-bit signal given when the data has to be written into the FIFO.

- Read: 1-bit signal given when the data has to be read from the FIFO.

### Output Signals

- Output Data: 8 bits 

- Full: 1-bit signal generated when the FIFO is full. 

- Empty: 1-bit signal generated when the FIFO is empty.

### Internal Signals

- Read Pointer: a 5-bit wire to keep track of the FIFO's index that has to be read

- Write Pointer: a 5-bit wire to keep track of the FIFO's index where the data should be written