https://github.com/saopayne/digital-alarm-clock

This is an implementation of a digital alarm clock in VHDL and tested out on the Altera DE2-70 FPGA Board.
https://github.com/saopayne/digital-alarm-clock

Last synced: 6 days ago
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This is an implementation of a digital alarm clock in VHDL and tested out on the Altera DE2-70 FPGA Board.

• Host: GitHub
• URL: https://github.com/saopayne/digital-alarm-clock
• Owner: saopayne
• Created: 2015-05-21T21:00:41.000Z (almost 10 years ago)
• Default Branch: master
• Last Pushed: 2015-05-21T21:12:21.000Z (almost 10 years ago)
• Last Synced: 2024-12-06T20:27:59.819Z (3 months ago)
• Language: VHDL
• Size: 25.6 MB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
 #Digital-Alarm-Clock implementation