https://github.com/sarwanshah/hu_2021_risc-v-architecture-verilog
In this project we implemented the RISC V processor architecture in Verilog.
https://github.com/sarwanshah/hu_2021_risc-v-architecture-verilog
computer-architecture processor-design risc-v verilog
Last synced: 8 months ago
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In this project we implemented the RISC V processor architecture in Verilog.
- Host: GitHub
- URL: https://github.com/sarwanshah/hu_2021_risc-v-architecture-verilog
- Owner: SarwanShah
- Created: 2025-02-08T22:16:28.000Z (8 months ago)
- Default Branch: main
- Last Pushed: 2025-02-10T00:38:43.000Z (8 months ago)
- Last Synced: 2025-02-10T01:27:16.249Z (8 months ago)
- Topics: computer-architecture, processor-design, risc-v, verilog
- Language: Verilog
- Homepage:
- Size: 10.7 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# Implementing RISC-V Architecture in Verilog
This project was developed under the EE-371 Computer Architecture course at Habib University during Spring 2021. This project involves the implementation of a **RISC-V processor architecture** using **Verilog** hardware description language. The RISC-V architecture is a free and open ISA enabling a new era of processor innovation through open standard collaboration.
## Project Features
- **Processor Core Design**: Implementation of the RISC-V processor core in Verilog.
- **Modular Design**: Organized code structure for different components of the processor.
- **Simulation Support**: Testbenches for simulating and verifying processor functionality.