https://github.com/sauravmaheshkar/verilog-template

A Template for Verilog Projects using iverilog and gtkwave.
https://github.com/sauravmaheshkar/verilog-template

hardware-description-language template-project verilog verilog-template vhdl

Last synced: 21 days ago
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A Template for Verilog Projects using iverilog and gtkwave.

• Host: GitHub
• URL: https://github.com/sauravmaheshkar/verilog-template
• Owner: SauravMaheshkar
• License: mit
• Created: 2023-10-21T00:20:40.000Z (about 1 year ago)
• Default Branch: main
• Last Pushed: 2024-06-23T08:46:29.000Z (5 months ago)
• Last Synced: 2024-06-23T09:41:41.921Z (5 months ago)
• Topics: hardware-description-language, template-project, verilog, verilog-template, vhdl
• Language: Makefile
• Homepage:
• Size: 15.6 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 1
• Metadata Files:
  • License: LICENSE
  • Codeowners: .github/CODEOWNERS

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