https://github.com/sauravmaheshkar/verilog-template

❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)
https://github.com/sauravmaheshkar/verilog-template

hardware-description-language template-project verilog verilog-template vhdl

Last synced: 9 days ago
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❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)

• Host: GitHub
• URL: https://github.com/sauravmaheshkar/verilog-template
• Owner: SauravMaheshkar
• License: mit
• Created: 2023-10-21T00:20:40.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2024-06-23T08:46:29.000Z (8 months ago)
• Last Synced: 2025-01-27T16:17:54.169Z (14 days ago)
• Topics: hardware-description-language, template-project, verilog, verilog-template, vhdl
• Language: Makefile
• Homepage:
• Size: 15.6 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 2
• Metadata Files:
  • Readme: .github/README.md
  • License: LICENSE
  • Codeowners: .github/CODEOWNERS

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README

        
[![built with nix](https://builtwithnix.org/badge.svg)](https://builtwithnix.org)

A Template for Verilog Projects (using `iverilog` and `gtkwave`).

* All test-bench's must be named as `*_tb.v` and be placed within the `tests/` dir.

* This template includes a recommended extension for vscode and the necessary settings to make the extension work with the provided directory structure.

* The `Makefile` is inspired from [@pwmarcz's work](https://github.com/pwmarcz/fpga-tools/blob/master/fpga.mk).