https://github.com/secworks/verilator_template

(Hopefully) simple template for a Verilator SystemVerilog project with a usable testbench
https://github.com/secworks/verilator_template

Last synced: 2 months ago
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(Hopefully) simple template for a Verilator SystemVerilog project with a usable testbench

• Host: GitHub
• URL: https://github.com/secworks/verilator_template
• Owner: secworks
• License: bsd-2-clause
• Created: 2023-12-24T10:13:27.000Z (about 1 year ago)
• Default Branch: main
• Last Pushed: 2024-02-06T21:40:55.000Z (12 months ago)
• Last Synced: 2024-08-03T01:39:40.830Z (6 months ago)
• Language: Verilog
• Size: 5.86 KB
• Stars: 6
• Watchers: 3
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# verilator_template

(Hopefully) simple template for a Verilator SystemVerilog project with

a usable testbench.

We want to have a template that generates a clock and a reset that

drives a testbench that instantiates a simple DUT. The testbench

should be able to feed the DUT with test vectors and probe the

internal state of the DUT.

This can then be used as basis for other design.

Cornucopia

Somebody, please THINK of the 4711 children!